From b43c2e895289b20f84fc0c86e25d16ba6e9be29f Mon Sep 17 00:00:00 2001 From: Kevin Kirspel Date: Tue, 24 Jan 2017 09:40:31 -0500 Subject: Adding ARM VFP V2 support --- c/src/lib/libbsp/arm/shared/start/start.S | 4 ++++ cpukit/score/cpu/arm/rtems/score/arm.h | 6 ++++++ 2 files changed, 10 insertions(+) mode change 100644 => 100755 c/src/lib/libbsp/arm/shared/start/start.S mode change 100644 => 100755 cpukit/score/cpu/arm/rtems/score/arm.h diff --git a/c/src/lib/libbsp/arm/shared/start/start.S b/c/src/lib/libbsp/arm/shared/start/start.S old mode 100644 new mode 100755 index 7adcb443c2..c5263ece7b --- a/c/src/lib/libbsp/arm/shared/start/start.S +++ b/c/src/lib/libbsp/arm/shared/start/start.S @@ -274,6 +274,7 @@ bsp_start_skip_hyp_svc_switch: /* Stay in SVC mode */ #ifdef ARM_MULTILIB_VFP +#ifdef ARM_MULTILIB_HAS_CPACR /* Read CPACR */ mrc p15, 0, r0, c1, c0, 2 @@ -289,6 +290,7 @@ bsp_start_skip_hyp_svc_switch: /* Write CPACR */ mcr p15, 0, r0, c1, c0, 2 isb +#endif /* Enable FPU */ mov r0, #(1 << 30) @@ -408,6 +410,7 @@ _start: #endif #ifdef ARM_MULTILIB_VFP +#ifdef ARM_MULTILIB_HAS_CPACR /* * Enable CP10 and CP11 coprocessors for privileged and user mode in * CPACR (bits 20-23). Ensure that write to register completes. @@ -418,6 +421,7 @@ _start: str r1, [r0] dsb isb +#endif #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION bl bsp_start_init_registers_vfp diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h old mode 100644 new mode 100755 index 666ee54068..f08da1dc57 --- a/cpukit/score/cpu/arm/rtems/score/arm.h +++ b/cpukit/score/cpu/arm/rtems/score/arm.h @@ -58,6 +58,12 @@ extern "C" { #define ARM_MULTILIB_CACHE_LINE_MAX_64 #endif +#if defined(__ARM_ARCH_7A__) \ + || defined(__ARM_ARCH_7M__) \ + || defined(__ARM_ARCH_7EM__) + #define ARM_MULTILIB_HAS_CPACR +#endif + #if !defined(__SOFTFP__) #if defined(__ARM_NEON__) #define ARM_MULTILIB_VFP_D32 -- cgit v1.2.3