From 9bd7b3b1a26adc41678ec4d4a1d97f057cdb43a7 Mon Sep 17 00:00:00 2001 From: Daniel Hellstrom Date: Tue, 20 May 2014 17:45:07 +0200 Subject: SPARC: Fatal_halt use source and exit codes The Fatal_halt handler now have two options, either halt as before or enter system error state to return to debugger or simulator. The exit-code is now also propagated to the debugger which is very useful for testing. The CPU_Fatal_halt handler was split up into two, since the only the LEON3 support the CPU power down. The LEON3 halt now uses the power-down instruction to save CPU power. This doesn't stop a potential watch-dog timer from expiring. --- c/src/lib/libbsp/sparc/erc32/Makefile.am | 1 + c/src/lib/libbsp/sparc/erc32/configure.ac | 5 +++ c/src/lib/libbsp/sparc/leon2/Makefile.am | 1 + c/src/lib/libbsp/sparc/leon2/configure.ac | 5 +++ c/src/lib/libbsp/sparc/leon3/Makefile.am | 1 + c/src/lib/libbsp/sparc/leon3/configure.ac | 5 +++ .../libbsp/sparc/leon3/startup/bsp_fatal_halt.c | 36 ++++++++++++++++++++ .../libbsp/sparc/shared/startup/bsp_fatal_halt.c | 38 ++++++++++++++++++++++ cpukit/score/cpu/sparc/rtems/score/cpu.h | 10 ++---- 9 files changed, 94 insertions(+), 8 deletions(-) create mode 100644 c/src/lib/libbsp/sparc/leon3/startup/bsp_fatal_halt.c create mode 100644 c/src/lib/libbsp/sparc/shared/startup/bsp_fatal_halt.c diff --git a/c/src/lib/libbsp/sparc/erc32/Makefile.am b/c/src/lib/libbsp/sparc/erc32/Makefile.am index b9f1c5348e..00e398b54f 100644 --- a/c/src/lib/libbsp/sparc/erc32/Makefile.am +++ b/c/src/lib/libbsp/sparc/erc32/Makefile.am @@ -46,6 +46,7 @@ libbsp_a_SOURCES += startup/bspidle.c libbsp_a_SOURCES += startup/bspdelay.c libbsp_a_SOURCES += ../../sparc/shared/startup/early_malloc.c libbsp_a_SOURCES += ../../sparc/shared/startup/bsp_fatal_exit.c +libbsp_a_SOURCES += ../../sparc/shared/startup/bsp_fatal_halt.c # ISR Handler libbsp_a_SOURCES += ../../sparc/shared/cpu.c libbsp_a_SOURCES += ../../sparc/shared/irq_asm.S diff --git a/c/src/lib/libbsp/sparc/erc32/configure.ac b/c/src/lib/libbsp/sparc/erc32/configure.ac index 4cbfb7e3d4..72a75d1cfc 100644 --- a/c/src/lib/libbsp/sparc/erc32/configure.ac +++ b/c/src/lib/libbsp/sparc/erc32/configure.ac @@ -43,6 +43,11 @@ RTEMS_BSPOPTS_HELP([ENABLE_SIS_QUIRKS], BSP will be enabled. In particular, SIS requires special initialization not used on real ERC32 hardware.]) +RTEMS_BSPOPTS_SET([BSP_POWER_DOWN_AT_FATAL_HALT],[*],[]) +RTEMS_BSPOPTS_HELP([BSP_POWER_DOWN_AT_FATAL_HALT], +[If defined, CPU is spinning on fatal exit. Otherwise generate system + error which will hand over to debugger, simulator, etc.]) + RTEMS_BSP_CLEANUP_OPTIONS(0,1,1) # Explicitly list all Makefiles here diff --git a/c/src/lib/libbsp/sparc/leon2/Makefile.am b/c/src/lib/libbsp/sparc/leon2/Makefile.am index 3f8edf436b..ac6f327396 100644 --- a/c/src/lib/libbsp/sparc/leon2/Makefile.am +++ b/c/src/lib/libbsp/sparc/leon2/Makefile.am @@ -61,6 +61,7 @@ libbsp_a_SOURCES += ../../shared/bspinit.c libbsp_a_SOURCES += startup/bspdelay.c libbsp_a_SOURCES += ../../sparc/shared/startup/early_malloc.c libbsp_a_SOURCES += ../../sparc/shared/startup/bsp_fatal_exit.c +libbsp_a_SOURCES += ../../sparc/shared/startup/bsp_fatal_halt.c # ISR Handler libbsp_a_SOURCES += ../../sparc/shared/cpu.c diff --git a/c/src/lib/libbsp/sparc/leon2/configure.ac b/c/src/lib/libbsp/sparc/leon2/configure.ac index 610a04909c..dd49a17487 100644 --- a/c/src/lib/libbsp/sparc/leon2/configure.ac +++ b/c/src/lib/libbsp/sparc/leon2/configure.ac @@ -36,6 +36,11 @@ RTEMS_BSPOPTS_HELP([SIMSPARC_FAST_IDLE], time spent in the idle task is minimized. This significantly reduces the wall time required to execute the RTEMS test suites.]) +RTEMS_BSPOPTS_SET([BSP_POWER_DOWN_AT_FATAL_HALT],[*],[]) +RTEMS_BSPOPTS_HELP([BSP_POWER_DOWN_AT_FATAL_HALT], +[If defined, CPU is spinning on fatal exit. Otherwise generate system + error which will hand over to debugger, simulator, etc.]) + RTEMS_BSP_CLEANUP_OPTIONS(0, 1, 1) # Explicitly list all Makefiles here diff --git a/c/src/lib/libbsp/sparc/leon3/Makefile.am b/c/src/lib/libbsp/sparc/leon3/Makefile.am index b8079c64d1..fa297acdc4 100644 --- a/c/src/lib/libbsp/sparc/leon3/Makefile.am +++ b/c/src/lib/libbsp/sparc/leon3/Makefile.am @@ -42,6 +42,7 @@ libbsp_a_SOURCES += ../../shared/bspclean.c ../../shared/bsplibc.c \ libbsp_a_SOURCES += startup/bspreset.c libbsp_a_SOURCES += startup/cpucounter.c libbsp_a_SOURCES += ../../sparc/shared/startup/bsp_fatal_exit.c +libbsp_a_SOURCES += startup/bsp_fatal_halt.c # ISR Handler libbsp_a_SOURCES += ../../sparc/shared/cpu.c diff --git a/c/src/lib/libbsp/sparc/leon3/configure.ac b/c/src/lib/libbsp/sparc/leon3/configure.ac index 3fe1e48024..8ace8a30fd 100644 --- a/c/src/lib/libbsp/sparc/leon3/configure.ac +++ b/c/src/lib/libbsp/sparc/leon3/configure.ac @@ -38,6 +38,11 @@ RTEMS_BSPOPTS_HELP([BSP_LEON3_SMP], [Always defined when on a LEON3 to enable the LEON3 support for determining the CPU core number in an SMP configuration.]) +RTEMS_BSPOPTS_SET([BSP_POWER_DOWN_AT_FATAL_HALT],[*],[]) +RTEMS_BSPOPTS_HELP([BSP_POWER_DOWN_AT_FATAL_HALT], +[If defined, CPU is powered down on fatal exit. Otherwise generate system + error which will hand over to debugger, simulator, etc.]) + RTEMS_BSP_CLEANUP_OPTIONS(0, 1, 1) RTEMS_BSP_LINKCMDS diff --git a/c/src/lib/libbsp/sparc/leon3/startup/bsp_fatal_halt.c b/c/src/lib/libbsp/sparc/leon3/startup/bsp_fatal_halt.c new file mode 100644 index 0000000000..2f4bd3af33 --- /dev/null +++ b/c/src/lib/libbsp/sparc/leon3/startup/bsp_fatal_halt.c @@ -0,0 +1,36 @@ +/** + * @file + * @ingroup sparc_leon3 + * @brief LEON3 BSP Fatal_halt handler. + * + * COPYRIGHT (c) 2014. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include + +#ifdef BSP_POWER_DOWN_AT_FATAL_HALT + +/* Power down LEON CPU on fatal error exit */ +void _CPU_Fatal_halt(uint32_t source, uint32_t error) +{ + sparc_disable_interrupts(); + leon3_power_down_loop(); +} + +#else + +/* return to debugger, simulator, hypervisor or similar by exiting + * with an error code. g1=1, g2=FATAL_SOURCE, G3=error-code. + */ +void _CPU_Fatal_halt(uint32_t source, uint32_t error) +{ + sparc_syscall_exit(source, error); +} + +#endif diff --git a/c/src/lib/libbsp/sparc/shared/startup/bsp_fatal_halt.c b/c/src/lib/libbsp/sparc/shared/startup/bsp_fatal_halt.c new file mode 100644 index 0000000000..2cc7b6d836 --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/startup/bsp_fatal_halt.c @@ -0,0 +1,38 @@ +/** + * @file + * @ingroup sparc_bsp + * @brief ERC32/LEON2 BSP Fatal_halt handler. + * + * COPYRIGHT (c) 2014. + * Aeroflex Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#ifdef BSP_POWER_DOWN_AT_FATAL_HALT + +/* Spin CPU on fatal error exit */ +void _CPU_Fatal_halt(uint32_t source, uint32_t error) +{ + uint32_t level = sparc_disable_interrupts(); + + __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); + + while (1) ; /* loop forever */ +} + +#else + +/* return to debugger, simulator, hypervisor or similar by exiting + * with an error code. g1=1, g2=FATAL_SOURCE, G3=error-code. + */ +void _CPU_Fatal_halt(uint32_t source, uint32_t error) +{ + sparc_syscall_exit(source, error); +} + +#endif diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index 70d1785e54..6ce065cfe4 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -1080,14 +1080,8 @@ void _CPU_Context_Initialize( * location or a register, optionally disables interrupts, and * halts/stops the CPU. */ -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - uint32_t level; \ - \ - level = sparc_disable_interrupts(); \ - __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ - while (1); /* loop forever */ \ - } while (0) +extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) + RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; /* end of Fatal Error manager macros */ -- cgit v1.2.3