From 88f4d44f00ad11978a973f5f474ed8a92ffe3a98 Mon Sep 17 00:00:00 2001 From: Alan Cudmore Date: Sun, 18 Sep 2022 15:22:29 -0400 Subject: bsps/riscv/riscv: Fix fe310_uart_read Note: Resending after learning how to use git send-email, please disregard previous message. This fixes the riscv fe310 console driver fe310_uart_read function. The function reads the RX status/data register to check if data is available, but discards the data and reads it a seconds time. Also cleared the interrupt enable bit in the first_open function. Close #4719 --- bsps/riscv/riscv/console/fe310-uart.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/bsps/riscv/riscv/console/fe310-uart.c b/bsps/riscv/riscv/console/fe310-uart.c index 4ae62d7176..506521add0 100644 --- a/bsps/riscv/riscv/console/fe310-uart.c +++ b/bsps/riscv/riscv/console/fe310-uart.c @@ -34,11 +34,13 @@ int fe310_uart_read(rtems_termios_device_context *base) { fe310_uart_context * ctx = (fe310_uart_context*) base; + int32_t rxdata; - if ((ctx->regs->rxdata & TXRXREADY) != 0) { + rxdata = ctx->regs->rxdata; + if ((rxdata & TXRXREADY) != 0) { return -1; } else { - return ctx->regs->rxdata; + return rxdata & 0xFF; } } @@ -91,6 +93,7 @@ static bool fe310_uart_first_open ( (ctx->regs)->div = riscv_get_core_frequency() / 115200 - 1; (ctx->regs)->txctrl |= 1; (ctx->regs)->rxctrl |= 1; + (ctx->regs)->ie = 0; return true; }; -- cgit v1.2.3