From 819a6b35cc7ad4b3bc542e738c0933d55a132ccf Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Thu, 14 Jan 2016 08:07:06 +0100
Subject: arm: Honor cache for Cortex-M7 support

---
 cpukit/score/cpu/arm/armv7m-exception-handler-set.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
index d76dfa88b4..2718f80838 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
@@ -5,10 +5,10 @@
  */
 
 /*
- * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
+ * Copyright (c) 2011, 2016 Sebastian Huber.  All rights reserved.
  *
  *  embedded brains GmbH
- *  Obere Lagerstr. 30
+ *  Dornierstr. 4
  *  82178 Puchheim
  *  Germany
  *  <rtems@embedded-brains.de>
@@ -23,6 +23,7 @@
 #endif
 
 #include <rtems/score/armv7m.h>
+#include <rtems/rtems/cache.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
@@ -33,6 +34,14 @@ void _ARMV7M_Set_exception_handler(
 {
   if ( _ARMV7M_SCB->vtor [index] != handler ) {
     _ARMV7M_SCB->vtor [index] = handler;
+    rtems_cache_flush_multiple_data_lines(
+      &_ARMV7M_SCB->vtor [index],
+      sizeof(_ARMV7M_SCB->vtor [index])
+    );
+    rtems_cache_invalidate_multiple_instruction_lines(
+      &_ARMV7M_SCB->vtor [index],
+      sizeof(_ARMV7M_SCB->vtor [index])
+    );
   }
 }
 
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