From 65ee42ce8eb023c3459b01a21ff1192192d743c5 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Mon, 31 Jul 2017 13:39:34 +0200 Subject: bsp/qoriq: Simplify fatal exceptions Avoid use of small-data area, since it is not supported in the ELFv2 ABI by GCC. Update #3082. --- c/src/lib/libbsp/powerpc/qoriq/include/bsp.h | 2 + c/src/lib/libbsp/powerpc/qoriq/start/start.S | 200 +++++++++++------- c/src/lib/libbsp/powerpc/qoriq/startup/bspsmp.c | 14 +- c/src/lib/libbsp/powerpc/qoriq/startup/bspstart.c | 73 +++++-- .../lib/libbsp/powerpc/qoriq/startup/mmu-config.c | 2 +- c/src/lib/libcpu/powerpc/Makefile.am | 8 +- .../new-exceptions/bspsupport/ppc_exc_fatal.S | 228 +++++++++++++++++++++ c/src/lib/libcpu/powerpc/preinstall.am | 2 + 8 files changed, 420 insertions(+), 109 deletions(-) create mode 100644 c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_fatal.S diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/bsp.h b/c/src/lib/libbsp/powerpc/qoriq/include/bsp.h index 8e168ee71a..5a125e4a83 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/qoriq/include/bsp.h @@ -108,6 +108,8 @@ void qoriq_restart_secondary_processor( const qoriq_start_spin_table *spin_table ) RTEMS_NO_RETURN; +void qoriq_initialize_exceptions(void *interrupt_stack_begin); + #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/c/src/lib/libbsp/powerpc/qoriq/start/start.S b/c/src/lib/libbsp/powerpc/qoriq/start/start.S index 0dc303dfdb..7af2848720 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/start/start.S +++ b/c/src/lib/libbsp/powerpc/qoriq/start/start.S @@ -312,105 +312,149 @@ _start_secondary_processor: .section ".bsp_start_text", "ax" .align 4 bsp_exc_vector_base: - stw r1, ppc_exc_lock_crit@sdarel(r13) - stw r4, ppc_exc_vector_register_crit@sdarel(r13) - li r4, -32767 - b ppc_exc_wrap_bookE_crit + /* Critical input */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 2 - b ppc_exc_wrap_nopush_e500_mchk + stw r3, GPR3_OFFSET(r1) + li r3, 0 + b ppc_exc_fatal_critical + /* Machine check */ + stwu r1, -EXC_GENERIC_SIZE(r1) + stw r3, GPR3_OFFSET(r1) + li r3, 1 + b ppc_exc_fatal_machine_check + /* Data storage */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 3 - b ppc_exc_wrap_nopush_std + stw r3, GPR3_OFFSET(r1) + li r3, 2 + b ppc_exc_fatal_normal + /* Instruction storage */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 4 - b ppc_exc_wrap_nopush_std + stw r3, GPR3_OFFSET(r1) + li r3, 3 + b ppc_exc_fatal_normal + /* External input */ stwu r1, -CPU_INTERRUPT_FRAME_SIZE(r1) -#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER - stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) - li r4, -32763 -#endif b ppc_exc_wrap_async_normal -#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER nop nop -#endif + /* Alignment */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 6 - b ppc_exc_wrap_nopush_std + stw r3, GPR3_OFFSET(r1) + li r3, 5 + b ppc_exc_fatal_normal + /* Program */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 7 - b ppc_exc_wrap_nopush_std + stw r3, GPR3_OFFSET(r1) + li r3, 6 + b ppc_exc_fatal_normal +#ifdef __PPC_CPU_E6500__ + /* Floating-point unavailable */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 8 - b ppc_exc_wrap_nopush_std -system_call: + stw r3, GPR3_OFFSET(r1) + li r3, 7 + b ppc_exc_fatal_normal +#endif + /* System call */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 12 - b ppc_exc_wrap_nopush_std + stw r3, GPR3_OFFSET(r1) + li r3, 8 + b ppc_exc_fatal_normal +#ifdef __PPC_CPU_E6500__ + /* APU unavailable */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 24 - b ppc_exc_wrap_nopush_std - stwu r1, -CPU_INTERRUPT_FRAME_SIZE(r1) -#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER - stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) - li r4, -32752 + stw r3, GPR3_OFFSET(r1) + li r3, 9 + b ppc_exc_fatal_normal #endif - b ppc_exc_wrap_async_normal -#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER - nop - nop -#endif - stwu r1, -CPU_INTERRUPT_FRAME_SIZE(r1) -#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER - stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1) - li r4, -32749 -#endif - b ppc_exc_wrap_async_normal -#ifdef PPC_EXC_CONFIG_USE_FIXED_HANDLER - nop - nop + /* Decrementer */ + stwu r1, -EXC_GENERIC_SIZE(r1) + stw r3, GPR3_OFFSET(r1) + li r3, 10 + b ppc_exc_fatal_normal + /* Fixed-interval timer interrupt */ + stwu r1, -EXC_GENERIC_SIZE(r1) + stw r3, GPR3_OFFSET(r1) + li r3, 11 + b ppc_exc_fatal_normal + /* Watchdog timer interrupt */ + stwu r1, -EXC_GENERIC_SIZE(r1) + stw r3, GPR3_OFFSET(r1) + li r3, 12 + b ppc_exc_fatal_critical + /* Data TLB error */ + stwu r1, -EXC_GENERIC_SIZE(r1) + stw r3, GPR3_OFFSET(r1) + li r3, 13 + b ppc_exc_fatal_normal + /* Instruction TLB error */ + stwu r1, -EXC_GENERIC_SIZE(r1) + stw r3, GPR3_OFFSET(r1) + li r3, 14 + b ppc_exc_fatal_normal + /* Debug */ + stwu r1, -EXC_GENERIC_SIZE(r1) + stw r3, GPR3_OFFSET(r1) + li r3, 15 + b ppc_exc_fatal_debug + /* SPE APU unavailable or AltiVec unavailable */ + stwu r1, -EXC_GENERIC_SIZE(r1) + stw r3, GPR3_OFFSET(r1) + li r3, 32 + b ppc_exc_fatal_normal + /* SPE floating-point data exception or AltiVec assist */ + stwu r1, -EXC_GENERIC_SIZE(r1) + stw r3, GPR3_OFFSET(r1) + li r3, 33 + b ppc_exc_fatal_normal +#ifndef __PPC_CPU_E6500__ + /* SPE floating-point round exception */ + stwu r1, -EXC_GENERIC_SIZE(r1) + stw r3, GPR3_OFFSET(r1) + li r3, 34 + b ppc_exc_fatal_normal #endif - stw r1, ppc_exc_lock_crit@sdarel(r13) - stw r4, ppc_exc_vector_register_crit@sdarel(r13) - li r4, -32748 - b ppc_exc_wrap_bookE_crit + /* Performance monitor */ + stwu r1, -EXC_GENERIC_SIZE(r1) + stw r3, GPR3_OFFSET(r1) + li r3, 35 + b ppc_exc_fatal_normal +#ifdef __PPC_CPU_E6500__ + /* Processor doorbell interrupt */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 18 - b ppc_exc_wrap_nopush_std + stw r3, GPR3_OFFSET(r1) + li r3, 36 + b ppc_exc_fatal_normal + /* Processor doorbell critical interrupt */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 17 - b ppc_exc_wrap_nopush_std + stw r3, GPR3_OFFSET(r1) + li r3, 37 + b ppc_exc_fatal_critical + /* Guest processor doorbell */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 13 - b ppc_exc_wrap_nopush_bookE_crit + stw r3, GPR3_OFFSET(r1) + li r3, 38 + b ppc_exc_fatal_normal + /* Guest processor doorbell critical and machine check */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 10 - b ppc_exc_wrap_nopush_std + stw r3, GPR3_OFFSET(r1) + li r3, 39 + b ppc_exc_fatal_critical + /* Hypervisor system call */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 25 - b ppc_exc_wrap_nopush_std + stw r3, GPR3_OFFSET(r1) + li r3, 40 + b ppc_exc_fatal_normal + /* Hypervisor privilege */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 26 - b ppc_exc_wrap_nopush_std + stw r3, GPR3_OFFSET(r1) + li r3, 41 + b ppc_exc_fatal_normal + /* LRAT error */ stwu r1, -EXC_GENERIC_SIZE(r1) - stw r4, GPR4_OFFSET(r1) - li r4, 15 - b ppc_exc_wrap_nopush_std + stw r3, GPR3_OFFSET(r1) + li r3, 42 + b ppc_exc_fatal_normal +#endif /* Symbol provided for debugging and tracing */ bsp_exc_vector_end: diff --git a/c/src/lib/libbsp/powerpc/qoriq/startup/bspsmp.c b/c/src/lib/libbsp/powerpc/qoriq/startup/bspsmp.c index 56bfa9f26b..b0342ec9ec 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/startup/bspsmp.c +++ b/c/src/lib/libbsp/powerpc/qoriq/startup/bspsmp.c @@ -96,19 +96,7 @@ void bsp_start_on_secondary_processor(void) uint32_t cpu_index_self = _SMP_Get_current_processor(); const Per_CPU_Control *cpu_self = _Per_CPU_Get_by_index(cpu_index_self); - ppc_exc_initialize_with_vector_base( - (uintptr_t) cpu_self->interrupt_stack_low, - rtems_configuration_get_interrupt_stack_size(), - bsp_exc_vector_base - ); - - /* Now it is possible to make the code execute only */ - qoriq_mmu_change_perm( - FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX, - FSL_EIS_MAS3_SX, - FSL_EIS_MAS3_SR - ); - + qoriq_initialize_exceptions(cpu_self->interrupt_stack_low); bsp_interrupt_facility_initialize(); start_thread_if_necessary(cpu_index_self); diff --git a/c/src/lib/libbsp/powerpc/qoriq/startup/bspstart.c b/c/src/lib/libbsp/powerpc/qoriq/startup/bspstart.c index 7aba178806..58f930ee22 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/qoriq/startup/bspstart.c @@ -110,6 +110,63 @@ static void initialize_frequency_parameters(void) rtems_counter_initialize_converter(fdt32_to_cpu(*val_fdt)); } +#define MTIVPR(base) \ + __asm__ volatile ("mtivpr %0" : : "r" (base)) + +#define MTIVOR(vec, offset) \ + do { \ + __asm__ volatile ("mtspr " RTEMS_XSTRING(vec) ", %0" : : "r" (offset)); \ + offset += 16; \ + } while (0) + +void qoriq_initialize_exceptions(void *interrupt_stack_begin) +{ + uintptr_t addr; + + ppc_exc_initialize_interrupt_stack( + (uintptr_t) interrupt_stack_begin, + rtems_configuration_get_interrupt_stack_size() + ); + + addr = (uintptr_t) bsp_exc_vector_base; + MTIVPR(addr); + MTIVOR(BOOKE_IVOR0, addr); + MTIVOR(BOOKE_IVOR1, addr); + MTIVOR(BOOKE_IVOR2, addr); + MTIVOR(BOOKE_IVOR3, addr); + MTIVOR(BOOKE_IVOR4, addr); + MTIVOR(BOOKE_IVOR5, addr); + MTIVOR(BOOKE_IVOR6, addr); +#ifdef __PPC_CPU_E6500__ + MTIVOR(BOOKE_IVOR7, addr); +#endif + MTIVOR(BOOKE_IVOR8, addr); +#ifdef __PPC_CPU_E6500__ + MTIVOR(BOOKE_IVOR9, addr); +#endif + MTIVOR(BOOKE_IVOR10, addr); + MTIVOR(BOOKE_IVOR11, addr); + MTIVOR(BOOKE_IVOR12, addr); + MTIVOR(BOOKE_IVOR13, addr); + MTIVOR(BOOKE_IVOR14, addr); + MTIVOR(BOOKE_IVOR15, addr); + MTIVOR(BOOKE_IVOR32, addr); + MTIVOR(BOOKE_IVOR33, addr); +#ifndef __PPC_CPU_E6500__ + MTIVOR(BOOKE_IVOR34, addr); +#endif + MTIVOR(BOOKE_IVOR35, addr); +#ifdef __PPC_CPU_E6500__ + MTIVOR(BOOKE_IVOR36, addr); + MTIVOR(BOOKE_IVOR37, addr); + MTIVOR(BOOKE_IVOR38, addr); + MTIVOR(BOOKE_IVOR39, addr); + MTIVOR(BOOKE_IVOR40, addr); + MTIVOR(BOOKE_IVOR41, addr); + MTIVOR(BOOKE_IVOR42, addr); +#endif +} + void bsp_start(void) { unsigned long i = 0; @@ -140,21 +197,7 @@ void bsp_start(void) } } - /* Initialize exception handler */ - ppc_exc_initialize_with_vector_base( - (uintptr_t) bsp_section_work_begin, - rtems_configuration_get_interrupt_stack_size(), - bsp_exc_vector_base - ); - - /* Now it is possible to make the code execute only */ - qoriq_mmu_change_perm( - FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX, - FSL_EIS_MAS3_SX, - FSL_EIS_MAS3_SR - ); - - /* Initalize interrupt support */ + qoriq_initialize_exceptions(bsp_section_work_begin); bsp_interrupt_initialize(); rtems_cache_coherent_add_area( diff --git a/c/src/lib/libbsp/powerpc/qoriq/startup/mmu-config.c b/c/src/lib/libbsp/powerpc/qoriq/startup/mmu-config.c index 3e572302ab..f3375ee824 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/startup/mmu-config.c +++ b/c/src/lib/libbsp/powerpc/qoriq/startup/mmu-config.c @@ -48,7 +48,7 @@ typedef struct { .begin = (uint32_t) b, \ .size = (uint32_t) s, \ .mas2 = 0, \ - .mas3 = FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX \ + .mas3 = FSL_EIS_MAS3_SX \ } #define ENTRY_R(b, s) { \ diff --git a/c/src/lib/libcpu/powerpc/Makefile.am b/c/src/lib/libcpu/powerpc/Makefile.am index f7d7e64e5c..8315ff64a0 100644 --- a/c/src/lib/libcpu/powerpc/Makefile.am +++ b/c/src/lib/libcpu/powerpc/Makefile.am @@ -28,18 +28,22 @@ new_exceptions_rtems_cpu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) if !mpc5xx noinst_PROGRAMS += new-exceptions/exc_bspsupport.rel new_exceptions_exc_bspsupport_rel_SOURCES = \ + new-exceptions/bspsupport/ppc_exc_async_normal.S \ + new-exceptions/bspsupport/ppc_exc_fatal.S \ + new-exceptions/bspsupport/ppc_exc_print.c +if !qoriq +new_exceptions_exc_bspsupport_rel_SOURCES += \ new-exceptions/bspsupport/ppc-code-copy.c \ new-exceptions/bspsupport/ppc_exc.S \ - new-exceptions/bspsupport/ppc_exc_async_normal.S \ new-exceptions/bspsupport/ppc_exc_naked.S \ new-exceptions/bspsupport/ppc_exc_hdl.c \ new-exceptions/bspsupport/ppc_exc_initialize.c \ new-exceptions/bspsupport/ppc_exc_global_handler.c \ - new-exceptions/bspsupport/ppc_exc_print.c \ new-exceptions/bspsupport/ppc_exc_categories.c \ new-exceptions/bspsupport/ppc_exc_address.c \ new-exceptions/bspsupport/ppc_exc_alignment.c \ new-exceptions/bspsupport/ppc_exc_prologue.c +endif new_exceptions_exc_bspsupport_rel_CPPFLAGS = $(AM_CPPFLAGS) new_exceptions_exc_bspsupport_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_fatal.S b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_fatal.S new file mode 100644 index 0000000000..31774a792a --- /dev/null +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_fatal.S @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2011, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include + +#define SCRATCH_REGISTER_0 r3 +#define SCRATCH_REGISTER_1 r4 + + .global ppc_exc_fatal_normal + .global ppc_exc_fatal_critical + .global ppc_exc_fatal_machine_check + .global ppc_exc_fatal_debug + +ppc_exc_fatal_critical: + + stw SCRATCH_REGISTER_1, GPR4_OFFSET(r1) + mfcsrr0 SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) + mfcsrr1 SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) + b .Lppc_exc_fatal + +ppc_exc_fatal_machine_check: + + stw SCRATCH_REGISTER_1, GPR4_OFFSET(r1) + mfmcsrr0 SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) + mfmcsrr1 SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) + b .Lppc_exc_fatal + +ppc_exc_fatal_debug: + + stw SCRATCH_REGISTER_1, GPR4_OFFSET(r1) + mfspr SCRATCH_REGISTER_1, BOOKE_DSRR0 + stw SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) + mfspr SCRATCH_REGISTER_1, BOOKE_DSRR1 + stw SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) + b .Lppc_exc_fatal + +ppc_exc_fatal_normal: + + stw SCRATCH_REGISTER_1, GPR4_OFFSET(r1) + mfsrr0 SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1) + mfsrr1 SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1) + +.Lppc_exc_fatal: + + stw r3, EXCEPTION_NUMBER_OFFSET(r1) + mfcr SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, EXC_CR_OFFSET(r1) + mfctr SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, EXC_CTR_OFFSET(r1) + mfxer SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, EXC_XER_OFFSET(r1) + mflr SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, EXC_LR_OFFSET(r1) + stw r0, GPR0_OFFSET(r1) + stw r1, GPR1_OFFSET(r1) + stw r2, GPR2_OFFSET(r1) + stw r5, GPR5_OFFSET(r1) + stw r6, GPR6_OFFSET(r1) + stw r7, GPR7_OFFSET(r1) + stw r8, GPR8_OFFSET(r1) + stw r9, GPR9_OFFSET(r1) + stw r10, GPR10_OFFSET(r1) + stw r11, GPR11_OFFSET(r1) + stw r12, GPR12_OFFSET(r1) + stw r13, GPR13_OFFSET(r1) + stw r14, GPR14_OFFSET(r1) + stw r15, GPR15_OFFSET(r1) + stw r16, GPR16_OFFSET(r1) + stw r17, GPR17_OFFSET(r1) + stw r18, GPR18_OFFSET(r1) + stw r19, GPR19_OFFSET(r1) + stw r20, GPR20_OFFSET(r1) + stw r21, GPR21_OFFSET(r1) + stw r22, GPR22_OFFSET(r1) + stw r23, GPR23_OFFSET(r1) + stw r24, GPR24_OFFSET(r1) + stw r25, GPR25_OFFSET(r1) + stw r26, GPR26_OFFSET(r1) + stw r27, GPR27_OFFSET(r1) + stw r28, GPR28_OFFSET(r1) + stw r29, GPR29_OFFSET(r1) + stw r30, GPR30_OFFSET(r1) + stw r31, GPR31_OFFSET(r1) + + /* Enable FPU and/or AltiVec */ +#if defined(PPC_MULTILIB_FPU) || defined(PPC_MULTILIB_ALTIVEC) + mfmsr SCRATCH_REGISTER_1 +#ifdef PPC_MULTILIB_FPU + ori SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, MSR_FP +#endif +#ifdef PPC_MULTILIB_ALTIVEC + oris SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, MSR_VE >> 16 +#endif + mtmsr SCRATCH_REGISTER_1 + isync +#endif + +#ifdef PPC_MULTILIB_ALTIVEC + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(0) + stvx v0, r1, SCRATCH_REGISTER_1 + mfvscr v0 + li SCRATCH_REGISTER_1, PPC_EXC_VSCR_OFFSET + stvewx v0, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(1) + stvx v1, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(2) + stvx v2, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(3) + stvx v3, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(4) + stvx v4, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(5) + stvx v5, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(6) + stvx v6, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(7) + stvx v7, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(8) + stvx v8, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(9) + stvx v9, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(10) + stvx v10, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(11) + stvx v11, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(12) + stvx v12, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(13) + stvx v13, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(14) + stvx v14, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(15) + stvx v15, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(16) + stvx v16, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(17) + stvx v17, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(18) + stvx v18, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(19) + stvx v19, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(20) + stvx v20, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(21) + stvx v21, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(22) + stvx v22, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(23) + stvx v23, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(24) + stvx v24, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(25) + stvx v25, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(26) + stvx v26, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(27) + stvx v27, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(28) + stvx v28, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(29) + stvx v29, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(30) + stvx v30, r1, SCRATCH_REGISTER_1 + li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(31) + stvx v31, r1, SCRATCH_REGISTER_1 + mfvrsave SCRATCH_REGISTER_1 + stw SCRATCH_REGISTER_1, PPC_EXC_VRSAVE_OFFSET(r1) +#endif + +#ifdef PPC_MULTILIB_FPU + stfd f0, PPC_EXC_FR_OFFSET(0)(r1) + mffs f0 + stfd f0, PPC_EXC_FPSCR_OFFSET(r1) + stfd f1, PPC_EXC_FR_OFFSET(1)(r1) + stfd f2, PPC_EXC_FR_OFFSET(2)(r1) + stfd f3, PPC_EXC_FR_OFFSET(3)(r1) + stfd f4, PPC_EXC_FR_OFFSET(4)(r1) + stfd f5, PPC_EXC_FR_OFFSET(5)(r1) + stfd f6, PPC_EXC_FR_OFFSET(6)(r1) + stfd f7, PPC_EXC_FR_OFFSET(7)(r1) + stfd f8, PPC_EXC_FR_OFFSET(8)(r1) + stfd f9, PPC_EXC_FR_OFFSET(9)(r1) + stfd f10, PPC_EXC_FR_OFFSET(10)(r1) + stfd f11, PPC_EXC_FR_OFFSET(11)(r1) + stfd f12, PPC_EXC_FR_OFFSET(12)(r1) + stfd f13, PPC_EXC_FR_OFFSET(13)(r1) + stfd f14, PPC_EXC_FR_OFFSET(14)(r1) + stfd f15, PPC_EXC_FR_OFFSET(15)(r1) + stfd f16, PPC_EXC_FR_OFFSET(16)(r1) + stfd f17, PPC_EXC_FR_OFFSET(17)(r1) + stfd f18, PPC_EXC_FR_OFFSET(18)(r1) + stfd f19, PPC_EXC_FR_OFFSET(19)(r1) + stfd f20, PPC_EXC_FR_OFFSET(20)(r1) + stfd f21, PPC_EXC_FR_OFFSET(21)(r1) + stfd f22, PPC_EXC_FR_OFFSET(22)(r1) + stfd f23, PPC_EXC_FR_OFFSET(23)(r1) + stfd f24, PPC_EXC_FR_OFFSET(24)(r1) + stfd f25, PPC_EXC_FR_OFFSET(25)(r1) + stfd f26, PPC_EXC_FR_OFFSET(26)(r1) + stfd f27, PPC_EXC_FR_OFFSET(27)(r1) + stfd f28, PPC_EXC_FR_OFFSET(28)(r1) + stfd f29, PPC_EXC_FR_OFFSET(29)(r1) + stfd f30, PPC_EXC_FR_OFFSET(30)(r1) + stfd f31, PPC_EXC_FR_OFFSET(31)(r1) +#endif + + li r3, 9 + addi r4, r1, FRAME_LINK_SPACE + b _Terminate diff --git a/c/src/lib/libcpu/powerpc/preinstall.am b/c/src/lib/libcpu/powerpc/preinstall.am index 948cb3c5c9..a490597ec9 100644 --- a/c/src/lib/libcpu/powerpc/preinstall.am +++ b/c/src/lib/libcpu/powerpc/preinstall.am @@ -58,6 +58,8 @@ $(PROJECT_INCLUDE)/bsp/vectors.h: new-exceptions/bspsupport/vectors.h $(PROJECT_ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h +if !mpc5xx +endif if shared $(PROJECT_INCLUDE)/libcpu/io.h: shared/include/io.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/io.h -- cgit v1.2.3