From 5b88ec5b68b3773da09d78dae68d716e4f009215 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Thu, 8 Mar 2018 17:23:21 -0600 Subject: riscv/include/rtems/score/types.h: Eliminate this file Updates #3327. --- cpukit/score/cpu/riscv/headers.am | 1 - cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 5 +- cpukit/score/cpu/riscv/include/rtems/score/types.h | 70 ---------------------- 3 files changed, 4 insertions(+), 72 deletions(-) delete mode 100644 cpukit/score/cpu/riscv/include/rtems/score/types.h diff --git a/cpukit/score/cpu/riscv/headers.am b/cpukit/score/cpu/riscv/headers.am index b5d3295c33..ec53f7d400 100644 --- a/cpukit/score/cpu/riscv/headers.am +++ b/cpukit/score/cpu/riscv/headers.am @@ -12,4 +12,3 @@ include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h include_rtems_score_HEADERS += include/rtems/score/riscv-utility.h include_rtems_score_HEADERS += include/rtems/score/riscv.h -include_rtems_score_HEADERS += include/rtems/score/types.h diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 3f8af862bf..ada46ef9ee 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -39,8 +39,8 @@ extern "C" { #endif +#include #include /* pick up machine definitions */ -#include #include #ifndef ASM #include @@ -595,6 +595,9 @@ static inline void _CPU_Context_Set_is_executing( } #endif /* RTEMS_SMP */ +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + #endif /* ASM */ #ifdef __cplusplus diff --git a/cpukit/score/cpu/riscv/include/rtems/score/types.h b/cpukit/score/cpu/riscv/include/rtems/score/types.h deleted file mode 100644 index d1440fb319..0000000000 --- a/cpukit/score/cpu/riscv/include/rtems/score/types.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @file - * - * @brief RISC-V Architecture Types API - */ - -/* - * This include file contains type definitions pertaining to the - * RISC-V processor family. - * - * COPYRIGHT (c) 2014 Hesham Almatary - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void riscv_isr; -typedef void ( *riscv_isr_entry )( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -- cgit v1.2.3