From 529154bad207a42a6d0f03343c7e215eab97ced5 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue, 31 Jul 2018 09:15:00 +0200
Subject: bsp/riscv: Initialize FPU depending on ISA

Initialize fcsr to zero for a defined rounding mode.

Update #3433.
---
 bsps/riscv/riscv/start/start.S | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S
index 290c95a166..feb07feedf 100644
--- a/bsps/riscv/riscv/start/start.S
+++ b/bsps/riscv/riscv/start/start.S
@@ -48,9 +48,12 @@ SYM(_start):
 	LADDR	gp, __global_pointer$
 	.option	pop
 
-	/* Init FPU unit if it's there */
+	/* Init FPU */
+#ifdef __riscv_flen
 	li	t0, MSTATUS_FS
 	csrs	mstatus, t0
+	csrw	fcsr, zero
+#endif
 
 	/* Set exception handler */
 	LADDR	t0, _RISCV_Exception_handler
-- 
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