From 3d11c1e2afee49470deec48c0cdd773ed0ac5191 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 1 Aug 2018 10:06:37 +0200 Subject: bsp/riscv: Fix a synchronization issue for PLIC Update #3433. --- bsps/riscv/riscv/irq/irq.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c index a369a81e62..ea33a3239c 100644 --- a/bsps/riscv/riscv/irq/irq.c +++ b/bsps/riscv/riscv/irq/irq.c @@ -84,7 +84,15 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self) bsp_interrupt_handler_dispatch( RISCV_INTERRUPT_VECTOR_EXTERNAL(interrupt_index) ); + plic_hart_regs->claim_complete = interrupt_index; + + /* + * FIXME: It is not clear which fence is necessary here or if a fence is + * necessary at all. The goal is that the complete signal is somehow + * recognized by the PLIC before the next claim is issued. + */ + __asm__ volatile ("fence o, i" : : : "memory"); } } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) { #ifdef RTEMS_SMP -- cgit v1.2.3