From 3ac61e52627c62e1641f954688c4327ca2170dc5 Mon Sep 17 00:00:00 2001 From: "Jeffrey O. Hill" Date: Tue, 5 Feb 2013 18:10:32 +0100 Subject: nios2: Rename file --- cpukit/score/cpu/nios2/Makefile.am | 2 +- cpukit/score/cpu/nios2/irq.c | 137 --------------------------------- cpukit/score/cpu/nios2/nios2-iic-irq.c | 137 +++++++++++++++++++++++++++++++++ 3 files changed, 138 insertions(+), 138 deletions(-) delete mode 100644 cpukit/score/cpu/nios2/irq.c create mode 100644 cpukit/score/cpu/nios2/nios2-iic-irq.c diff --git a/cpukit/score/cpu/nios2/Makefile.am b/cpukit/score/cpu/nios2/Makefile.am index c2947dd855..28587d814f 100644 --- a/cpukit/score/cpu/nios2/Makefile.am +++ b/cpukit/score/cpu/nios2/Makefile.am @@ -19,7 +19,6 @@ include_rtems_score_HEADERS += rtems/score/types.h noinst_LIBRARIES = libscorecpu.a libscorecpu_a_SOURCES = -libscorecpu_a_SOURCES += irq.c libscorecpu_a_SOURCES += nios2-context-initialize.c libscorecpu_a_SOURCES += nios2-context-switch.S libscorecpu_a_SOURCES += nios2-eic-il-low-level.S @@ -27,6 +26,7 @@ libscorecpu_a_SOURCES += nios2-eic-rsie-low-level.S libscorecpu_a_SOURCES += nios2-exception-frame-print.c libscorecpu_a_SOURCES += nios2-fatal-halt.c libscorecpu_a_SOURCES += nios2-iic-low-level.S +libscorecpu_a_SOURCES += nios2-iic-irq.c libscorecpu_a_SOURCES += nios2-initialize.c libscorecpu_a_SOURCES += nios2-initialize-vectors.c libscorecpu_a_SOURCES += nios2-isr-get-level.c diff --git a/cpukit/score/cpu/nios2/irq.c b/cpukit/score/cpu/nios2/irq.c deleted file mode 100644 index 5750f1311f..0000000000 --- a/cpukit/score/cpu/nios2/irq.c +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file - * - * @brief NIOS2 Exception and Interrupt Handler - * - * @note Derived from c4x/irq.c - */ - -/* - * COPYRIGHT (c) 1989-2007. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include -#include -#include - -/* - * This routine provides the RTEMS interrupt management. - * - * Upon entry, interrupts are disabled - */ - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - unsigned long *_old_stack_ptr; -#endif - -register unsigned long *stack_ptr __asm__ ("sp"); - -RTEMS_INLINE_ROUTINE void __IIC_Handler(void) -{ - uint32_t active; - uint32_t mask; - uint32_t vector; - - /* - * Obtain from the interrupt controller a bit list of pending interrupts, - * and then process the highest priority interrupt. This process loops, - * loading the active interrupt list on each pass until ipending - * return zero. - * - * The maximum interrupt latency for the highest priority interrupt is - * reduced by finding out which interrupts are pending as late as possible. - * Consider the case where the high priority interupt is asserted during - * the interrupt entry sequence for a lower priority interrupt to see why - * this is the case. - */ - - active = _Nios2_Get_ctlreg_ipending(); - - while (active) - { - vector = 0; - mask = 1; - - /* - * Test each bit in turn looking for an active interrupt. Once one is - * found call it to clear the interrupt condition. - */ - - while (active) - { - if (active & mask) - { - if ( _ISR_Vector_table[ vector] ) - (*_ISR_Vector_table[ vector ])(vector, NULL); - active &= ~mask; - } - mask <<= 1; - ++vector; - }; - - active = _Nios2_Get_ctlreg_ipending(); - } - -} - -void __ISR_Handler(void) -{ - register uint32_t level; - - /* Interrupts are disabled upon entry to this Handler */ - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - if ( _ISR_Nest_level == 0 ) { - /* Install irq stack */ - _old_stack_ptr = stack_ptr; - stack_ptr = _CPU_Interrupt_stack_high - 4; - } -#endif - - _ISR_Nest_level++; - - _Thread_Dispatch_increment_disable_level(); - - __IIC_Handler(); - - /* Make sure that interrupts are disabled again */ - _CPU_ISR_Disable( level ); - - _Thread_Dispatch_decrement_disable_level(); - - _ISR_Nest_level--; - - if( _ISR_Nest_level == 0) { -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - stack_ptr = _old_stack_ptr; -#endif - - if( !_Thread_Dispatch_in_critical_section() ) - { - if ( _Thread_Dispatch_necessary ) { - _CPU_ISR_Enable( level ); - _Thread_Dispatch(); - /* may have switched to another task and not return here immed. */ - _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */ - } - } - } - - _CPU_ISR_Enable( level ); -} - -void __Exception_Handler(CPU_Exception_frame *efr) -{ - _CPU_Fatal_halt(0xECC0); -} diff --git a/cpukit/score/cpu/nios2/nios2-iic-irq.c b/cpukit/score/cpu/nios2/nios2-iic-irq.c new file mode 100644 index 0000000000..5750f1311f --- /dev/null +++ b/cpukit/score/cpu/nios2/nios2-iic-irq.c @@ -0,0 +1,137 @@ +/** + * @file + * + * @brief NIOS2 Exception and Interrupt Handler + * + * @note Derived from c4x/irq.c + */ + +/* + * COPYRIGHT (c) 1989-2007. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include +#include + +/* + * This routine provides the RTEMS interrupt management. + * + * Upon entry, interrupts are disabled + */ + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + unsigned long *_old_stack_ptr; +#endif + +register unsigned long *stack_ptr __asm__ ("sp"); + +RTEMS_INLINE_ROUTINE void __IIC_Handler(void) +{ + uint32_t active; + uint32_t mask; + uint32_t vector; + + /* + * Obtain from the interrupt controller a bit list of pending interrupts, + * and then process the highest priority interrupt. This process loops, + * loading the active interrupt list on each pass until ipending + * return zero. + * + * The maximum interrupt latency for the highest priority interrupt is + * reduced by finding out which interrupts are pending as late as possible. + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = _Nios2_Get_ctlreg_ipending(); + + while (active) + { + vector = 0; + mask = 1; + + /* + * Test each bit in turn looking for an active interrupt. Once one is + * found call it to clear the interrupt condition. + */ + + while (active) + { + if (active & mask) + { + if ( _ISR_Vector_table[ vector] ) + (*_ISR_Vector_table[ vector ])(vector, NULL); + active &= ~mask; + } + mask <<= 1; + ++vector; + }; + + active = _Nios2_Get_ctlreg_ipending(); + } + +} + +void __ISR_Handler(void) +{ + register uint32_t level; + + /* Interrupts are disabled upon entry to this Handler */ + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + if ( _ISR_Nest_level == 0 ) { + /* Install irq stack */ + _old_stack_ptr = stack_ptr; + stack_ptr = _CPU_Interrupt_stack_high - 4; + } +#endif + + _ISR_Nest_level++; + + _Thread_Dispatch_increment_disable_level(); + + __IIC_Handler(); + + /* Make sure that interrupts are disabled again */ + _CPU_ISR_Disable( level ); + + _Thread_Dispatch_decrement_disable_level(); + + _ISR_Nest_level--; + + if( _ISR_Nest_level == 0) { +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + stack_ptr = _old_stack_ptr; +#endif + + if( !_Thread_Dispatch_in_critical_section() ) + { + if ( _Thread_Dispatch_necessary ) { + _CPU_ISR_Enable( level ); + _Thread_Dispatch(); + /* may have switched to another task and not return here immed. */ + _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */ + } + } + } + + _CPU_ISR_Enable( level ); +} + +void __Exception_Handler(CPU_Exception_frame *efr) +{ + _CPU_Fatal_halt(0xECC0); +} -- cgit v1.2.3