From 32b4a0c42704f0076da8e2d5411290f55d1b2965 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 9 Jun 2017 07:25:02 +0200 Subject: Simplify TLS support in context switch There is no need to save the thread pointer in _CPU_Context_switch() since it is a thread invariant. It is initialized once in _CPU_Context_Initialize(). --- c/src/lib/libbsp/sparc/shared/irq_asm.S | 6 +++++- c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S | 1 - cpukit/score/cpu/arm/cpu_asm.S | 13 ++----------- 3 files changed, 7 insertions(+), 13 deletions(-) diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S b/c/src/lib/libbsp/sparc/shared/irq_asm.S index 3d83431e54..075c7808d3 100644 --- a/c/src/lib/libbsp/sparc/shared/irq_asm.S +++ b/c/src/lib/libbsp/sparc/shared/irq_asm.S @@ -59,7 +59,11 @@ PUBLIC(_CPU_Context_switch) SYM(_CPU_Context_switch): st %g5, [%o0 + G5_OFFSET] ! save the global registers - st %g7, [%o0 + G7_OFFSET] + + /* + * No need to save the thread pointer %g7 since it is a thread + * invariant. It is initialized once in _CPU_Context_Initialize(). + */ std %l0, [%o0 + L0_OFFSET] ! save the local registers std %l2, [%o0 + L2_OFFSET] diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S b/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S index c0e11da076..1289813f2e 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S @@ -336,7 +336,6 @@ PROC (_CPU_Context_switch): PPC_GPR_STORE r30, PPC_CONTEXT_OFFSET_GPR30(r3) PPC_GPR_STORE r31, PPC_CONTEXT_OFFSET_GPR31(r3) - stw r2, PPC_CONTEXT_OFFSET_GPR2(r3) stw r11, PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE(r3) #ifdef PPC_MULTILIB_ALTIVEC diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S index 52ea77aae1..f58b99dc6c 100644 --- a/cpukit/score/cpu/arm/cpu_asm.S +++ b/cpukit/score/cpu/arm/cpu_asm.S @@ -56,24 +56,15 @@ DEFINE_FUNCTION_ARM(_CPU_Context_switch) /* Start saving context */ GET_SELF_CPU_CONTROL r2 + ldr r3, [r2, #PER_CPU_ISR_DISPATCH_DISABLE] stm r0, {r4, r5, r6, r7, r8, r9, r10, r11, r13, r14} -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER - mrc p15, 0, r3, c13, c0, 3 -#endif - - ldr r4, [r2, #PER_CPU_ISR_DISPATCH_DISABLE] - #ifdef ARM_MULTILIB_VFP add r5, r0, #ARM_CONTEXT_CONTROL_D8_OFFSET vstm r5, {d8-d15} #endif -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER - str r3, [r0, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET] -#endif - - str r4, [r0, #ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE] + str r3, [r0, #ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE] #ifdef RTEMS_SMP /* -- cgit v1.2.3