From 0659b5dea8d237d87857163ce96893b1a7495ad1 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Thu, 16 Oct 2014 16:20:22 -0500 Subject: powerpc/mvme5500: Fix warnings --- .../libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c | 144 +++++++++++---------- .../libbsp/powerpc/mvme5500/GT64260/MVME5500I2C.c | 52 ++++---- c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h | 115 +++++++++------- c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c | 141 ++++++++++---------- c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c | 2 - .../libbsp/powerpc/mvme5500/pci/pcifinddevice.c | 71 +++++----- .../powerpc/mvme5500/startup/pgtbl_activate.c | 44 ++++--- 7 files changed, 295 insertions(+), 274 deletions(-) diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c index c0f34b38c7..6b5b46e511 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c @@ -1,5 +1,8 @@ -/* GT64260TWSI.c : Two-Wire Serial Interface (TWSI) support for the GT64260 - * +/* + * Two-Wire Serial Interface (TWSI) support for the GT64260 + */ + +/* * Copyright (c) 2004, Brookhaven National Laboratory and * Shuchen Kate Feng * All rights reserved. @@ -15,11 +18,11 @@ * * We need it to read out I2C devices used for the MVME5500 * (eg. the memory SPD and VPD). - * */ + #include /*registers.h included here for rtems_bsp_delay()*/ #include -#include /* printk */ +#include #include "bsp/gtreg.h" #include "bsp/GT64260TWSI.h" @@ -28,44 +31,44 @@ #define TWSI_DEBUG 0 -static int TWSI_initFlg = 0; /* TWSI Initialization Flag */ +static int TWSI_initFlg = 0; /* TWSI Initialization Flag */ void GT64260TWSIinit(void) { - - if ( !TWSI_initFlg) { + if ( !TWSI_initFlg ) { #if TWSI_DEBUG - printk("GT64260TWSIinit("); + printk("GT64260TWSIinit("); #endif - outl( 0, TWSI_SFT_RST); /* soft reset */ - rtems_bsp_delay(1000); - - /* See 24.2.5 : Assume bus speed is 133MHZ - * Try to be close to the default frequency : 62.5KHZ - * value 0x2c: 69.27 KHz TWSI bus clock - */ - outl(0x2c, TWSI_BAUDE_RATE); - rtems_bsp_delay(1000); - - /* Set Acknowledge and enable TWSI in the Control register */ - outl(0x44, TWSI_CTRL); - rtems_bsp_delay(4000); - TWSI_initFlg = 1; + outl( 0, TWSI_SFT_RST); /* soft reset */ + rtems_bsp_delay(1000); + + /* See 24.2.5 : Assume bus speed is 133MHZ + * Try to be close to the default frequency : 62.5KHZ + * value 0x2c: 69.27 KHz TWSI bus clock + */ + outl(0x2c, TWSI_BAUDE_RATE); + rtems_bsp_delay(1000); + + /* Set Acknowledge and enable TWSI in the Control register */ + outl(0x44, TWSI_CTRL); + rtems_bsp_delay(4000); + TWSI_initFlg = 1; #if TWSI_DEBUG - printk(")\n"); + printk(")\n"); #endif } } /* return the interrupt flag */ -int GT64260TWSIintFlag(void) +static int GT64260TWSIintFlag(void) { unsigned int loop; for (loop = 0; loop < MAX_LOOP; loop++ ) { /* Return 1 if the interrupt flag is set */ - if (inl(TWSI_CTRL) & TWSI_INTFLG) return(1); - rtems_bsp_delay(1000); + if (inl(TWSI_CTRL) & TWSI_INTFLG) + return(1); + rtems_bsp_delay(1000); } return(0); } @@ -111,19 +114,19 @@ int GT64260TWSIstart(void) rtems_bsp_delay(1000); if (GT64260TWSIintFlag()) { - /* Check for completion of START sequence */ - for (loop = 0; loop * All rights reserved. * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution. - * - * To read information of the EEPROM via the I2C */ -#include /* printk */ +#include +#include /* printk */ #include /* uint32_t */ #include "bsp/GT64260TWSI.h" @@ -28,28 +30,34 @@ static unsigned char I2cDevByteAddr(uint32_t devA2A1A0, unsigned char byteNum) /**************************************************************************** * I2Cread_eeprom - read EEPROM VPD from the I2C */ -int I2Cread_eeprom(unsigned char I2cBusAddr,uint32_t devA2A1A0,uint32_t AddrBytes,unsigned char *pBuff,uint32_t numBytes) +int I2Cread_eeprom( + unsigned char I2cBusAddr, + uint32_t devA2A1A0, + uint32_t AddrBytes, + unsigned char *pBuff, + uint32_t numBytes +) { int status=0, lastByte=0; switch (AddrBytes) { case 1: if ((status=GT64260TWSIstart()) != -1) { - if ((status=GT64260TWSIwrite(I2cAddrPack(I2cBusAddr,devA2A1A0)))!= -1){ - if ((status=GT64260TWSIwrite(devA2A1A0))!=-1){ - if ((status=GT64260TWSIstart())!=-1) - status=GT64260TWSIwrite(I2cAddrPack((I2cBusAddr|0x01),devA2A1A0)); - } + if ((status=GT64260TWSIwrite(I2cAddrPack(I2cBusAddr,devA2A1A0)))!= -1){ + if ((status=GT64260TWSIwrite(devA2A1A0))!=-1){ + if ((status=GT64260TWSIstart())!=-1) + status=GT64260TWSIwrite(I2cAddrPack((I2cBusAddr|0x01),devA2A1A0)); + } } } break; case 2: if ((status=GT64260TWSIstart())!=-1) { - if ((status=GT64260TWSIwrite(I2cBusAddr))!= -1) { - if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,1)))!=-1) { - if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,0)))!= -1){ - if ((status=GT64260TWSIstart()) != -1) { - status = GT64260TWSIwrite((I2cBusAddr | 0x01)); + if ((status=GT64260TWSIwrite(I2cBusAddr))!= -1) { + if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,1)))!=-1) { + if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,0)))!= -1){ + if ((status=GT64260TWSIstart()) != -1) { + status = GT64260TWSIwrite((I2cBusAddr | 0x01)); } } } @@ -58,12 +66,12 @@ int I2Cread_eeprom(unsigned char I2cBusAddr,uint32_t devA2A1A0,uint32_t AddrByte break; case 3: if ((status = GT64260TWSIstart())!= -1) { - if ((status = GT64260TWSIwrite(I2cBusAddr))!= -1) { - if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,2)))!= -1){ - if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,1)))!= -1){ - if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,0)))!= -1){ - if ((status=GT64260TWSIstart())!= -1) { - status = GT64260TWSIwrite(I2cBusAddr | 0x01); + if ((status = GT64260TWSIwrite(I2cBusAddr))!= -1) { + if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,2)))!= -1){ + if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,1)))!= -1){ + if ((status=GT64260TWSIwrite(I2cDevByteAddr(devA2A1A0,0)))!= -1){ + if ((status=GT64260TWSIstart())!= -1) { + status = GT64260TWSIwrite(I2cBusAddr | 0x01); } } } diff --git a/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h b/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h index 972835a8cb..ad2249508c 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h @@ -1,6 +1,4 @@ /* - * bsp.h -- contain BSP API definition. - * * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr * * The license and distribution terms for this file may be @@ -8,13 +6,13 @@ * http://www.rtems.org/license/LICENSE. * * (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. - * - * */ #ifndef _BSP_H #define _BSP_H +#ifndef ASM + #include #include @@ -26,42 +24,42 @@ /* Board type */ typedef enum { - undefined = 0, - MVME5500, - MVME6100 + undefined = 0, + MVME5500, + MVME6100 } BSP_BoardTypes; -BSP_BoardTypes BSP_getBoardType(); +BSP_BoardTypes BSP_getBoardType(void); /* Board type */ typedef enum { - Undefined, - UNIVERSE2, - TSI148, + Undefined, + UNIVERSE2, + TSI148, } BSP_VMEchipTypes; -BSP_VMEchipTypes BSP_getVMEchipType(); +BSP_VMEchipTypes BSP_getVMEchipType(void); /* The version of Discovery system controller */ typedef enum { - notdefined, - GT64260A, - GT64260B, - MV64360, + notdefined, + GT64260A, + GT64260B, + MV64360, } DiscoveryChipVersion; -DiscoveryChipVersion BSP_getDiscoveryChipVersion(); +DiscoveryChipVersion BSP_getDiscoveryChipVersion(void); #define _256M 0x10000000 #define _512M 0x20000000 -#define GT64x60_REG_BASE 0xf1000000 /* Base of GT64260 Reg Space */ -#define GT64x60_REG_SPACE_SIZE 0x10000 /* 64Kb Internal Reg Space */ +#define GT64x60_REG_BASE 0xf1000000 /* Base of GT64260 Reg Space */ +#define GT64x60_REG_SPACE_SIZE 0x10000 /* 64Kb Internal Reg Space */ #define GT64x60_DEV1_BASE 0xf1100000 /* Device bank1(chip select 1) base */ -#define GT64260_DEV1_SIZE 0x00100000 /* Device bank size */ +#define GT64260_DEV1_SIZE 0x00100000 /* Device bank size */ /* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */ #define _IO_BASE GT64x60_REG_BASE @@ -69,10 +67,10 @@ DiscoveryChipVersion BSP_getDiscoveryChipVersion(); #define BSP_NVRAM_BASE_ADDR 0xf1110000 #define BSP_RTC_INTA_REG 0x7ff0 -#define BSP_RTC_SECOND 0x7ff2 -#define BSP_RTC_MINUTE 0x7ff3 -#define BSP_RTC_HOUR 0x7ff4 -#define BSP_RTC_DATE 0x7ff5 +#define BSP_RTC_SECOND 0x7ff2 +#define BSP_RTC_MINUTE 0x7ff3 +#define BSP_RTC_HOUR 0x7ff4 +#define BSP_RTC_DATE 0x7ff5 #define BSP_RTC_INTERRUPTS 0x7ff6 #define BSP_RTC_WATCHDOG 0x7ff7 @@ -81,15 +79,15 @@ DiscoveryChipVersion BSP_getDiscoveryChipVersion(); #define PCI1_IO_BASE 0xf0800000 /* PCI 0 memory space as seen from the CPU */ -#define PCI0_MEM_BASE 0x80000000 -#define PCI_MEM_BASE 0 /* glue for vmeUniverse */ +#define PCI0_MEM_BASE 0x80000000 +#define PCI_MEM_BASE 0 /* glue for vmeUniverse */ #define PCI_MEM_BASE_ADJUSTMENT 0 /* address of our ram on the PCI bus */ -#define PCI_DRAM_OFFSET 0 +#define PCI_DRAM_OFFSET 0 /* PCI 1 memory space as seen from the CPU */ -#define PCI1_MEM_BASE 0xe0000000 +#define PCI1_MEM_BASE 0xe0000000 #define PCI1_MEM_SIZE 0x10000000 /* Needed for hot adding via PMCspan on the PCI0 local bus. @@ -114,11 +112,11 @@ DiscoveryChipVersion BSP_getDiscoveryChipVersion(); #define BSP_INTERRUPT_STACK_SIZE (16 * 1024) /* 2/09 wants it to be adjustable by BSP */ /* uart.c uses out_8 instead of outb */ -#define BSP_UART_IOBASE_COM1 GT64x60_DEV1_BASE + 0x20000 -#define BSP_UART_IOBASE_COM2 GT64x60_DEV1_BASE + 0x21000 +#define BSP_UART_IOBASE_COM1 GT64x60_DEV1_BASE + 0x20000 +#define BSP_UART_IOBASE_COM2 GT64x60_DEV1_BASE + 0x21000 -#define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ -#define BSP_UART_BAUD_BASE 115200 +#define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ +#define BSP_UART_BAUD_BASE 115200 /* * Total memory using RESIDUAL DATA @@ -140,43 +138,72 @@ extern unsigned int BSP_time_base_divisor; #define BSP_Convert_decrementer( _value ) \ ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) -extern rtems_configuration_table BSP_Configuration; extern void BSP_panic(char *s); extern void bsp_reset(void); /* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ -extern int BSP_disconnect_clock_handler (void); -extern int BSP_connect_clock_handler (void); +extern int BSP_disconnect_clock_handler(void); +extern int BSP_connect_clock_handler(void); -extern unsigned long _BSP_clear_hostbridge_errors(); +unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); + +/* + * Prototypes for methods called only from .S for dependency tracking + */ +char *save_boot_params( + void *r3, + void *r4, + void *r5, + char *cmdline_start, + char *cmdline_end +); +void zero_bss(void); + +/* + * Prototypes for methods in the BSP that cross file boundaries + */ +uint32_t probeMemoryEnd(void); +void pci_interface(void); +void BSP_printPicIsrTbl(void); +int I2Cread_eeprom( + unsigned char I2cBusAddr, + uint32_t devA2A1A0, + uint32_t AddrBytes, + unsigned char *pBuff, + uint32_t numBytes +); #if 0 -#define RTEMS_BSP_NETWORK_DRIVER_NAME "gt1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_GT64260eth_driver_attach +#define RTEMS_BSP_NETWORK_DRIVER_NAME "gt1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_GT64260eth_driver_attach #else -#define RTEMS_BSP_NETWORK_DRIVER_NAME "wmG1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_i82544EI_driver_attach +#define RTEMS_BSP_NETWORK_DRIVER_NAME "wmG1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_i82544EI_driver_attach #endif extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH(); #define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER() -static inline void lwmemBar() +static inline void lwmemBar(void) { __asm__ volatile("lwsync":::"memory"); } -static inline void io_flush() +static inline void io_flush(void) { __asm__ volatile("isync":::"memory"); } -static inline void memBar() + +static inline void memBar(void) { __asm__ volatile("sync":::"memory"); } -static inline void ioBar() + +static inline void ioBar(void) { __asm__ volatile("eieio":::"memory"); } #endif + +#endif /* !ASM */ diff --git a/c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c b/c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c index a95425d480..0f99deed77 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c @@ -1,7 +1,8 @@ -/* BSP_irq.c - * +/* * This file contains the implementation of the function described in irq.h - * + */ + +/* * Copyright (C) 1998, 1999 valette@crf.canon.fr * * The license and distribution terms for this file may be @@ -319,11 +320,6 @@ void BSP_enable_irq_at_pic(const rtems_irq_number irqNum) rtems_interrupt_enable(level); } -void BSP_enable_pic_irq(const rtems_irq_number irqNum) -{ - BSP_enable_irq_at_pic(irqNum); -} - int BSP_disable_irq_at_pic(const rtems_irq_number irqNum) { int rval; @@ -331,7 +327,7 @@ int BSP_disable_irq_at_pic(const rtems_irq_number irqNum) unsigned int level; if ( ! is_pic_irq(irqNum) ) - return -1; + return -1; bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32; regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5; @@ -354,85 +350,80 @@ int BSP_disable_irq_at_pic(const rtems_irq_number irqNum) return rval ? 1 : 0; } -void BSP_disable_pic_irq(const rtems_irq_number irqNum) -{ - (void)BSP_disable_irq_at_pic(irqNum); -} - /* Use shared/irq : 2008 */ int BSP_setup_the_pic(rtems_irq_global_settings* config) { - int i; - - BSP_config = *config; - default_rtems_hdl = config->defaultEntry.hdl; - rtems_hdl_tbl = config->irqHdlTbl; - - /* Get ready for discovery BSP */ - BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_LO); - BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_HI); - BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_LO); - BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_HI); - BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Interrupt_Mask); - BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Value); - - /* Page 401, Table 598: - * Comm Unit Arbiter Control register : - * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0). - * MOTload default is set as level sensitive(1). Set it agin to make sure. - */ - out_le32((volatile unsigned int *)GT_CommUnitArb_Ctrl, - (in_le32((volatile unsigned int *)GT_CommUnitArb_Ctrl)| (1<<10))); + int i; + + BSP_config = *config; + default_rtems_hdl = config->defaultEntry.hdl; + rtems_hdl_tbl = config->irqHdlTbl; + + /* Get ready for discovery BSP */ + BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_LO); + BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_HI); + BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_LO); + BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_HI); + BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Interrupt_Mask); + BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Value); + + /* Page 401, Table 598: + * Comm Unit Arbiter Control register : + * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0). + * MOTload default is set as level sensitive(1). Set it agin to make sure. + */ + out_le32((volatile unsigned int *)GT_CommUnitArb_Ctrl, + (in_le32((volatile unsigned int *)GT_CommUnitArb_Ctrl)| (1<<10))); #if 0 - printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", - in_le32(BSP_irqMask_reg[0]), - in_le32(BSP_irqCause_reg[0])); - printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n", - in_le32(BSP_irqMask_reg[1]), - in_le32(BSP_irqCause_reg[1])); - printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n", - in_le32(BSP_irqMask_reg[2]), - in_le32(BSP_irqCause_reg[2])); + printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", + in_le32(BSP_irqMask_reg[0]), + in_le32(BSP_irqCause_reg[0])); + printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n", + in_le32(BSP_irqMask_reg[1]), + in_le32(BSP_irqCause_reg[1])); + printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n", + in_le32(BSP_irqMask_reg[2]), + in_le32(BSP_irqCause_reg[2])); #endif - /* Initialize the interrupt related registers */ - for (i=0; i<3; i++) { - out_le32(BSP_irqCause_reg[i], 0); - out_le32(BSP_irqMask_reg[i], 0); - } - in_le32(BSP_irqMask_reg[2]); - compute_pic_masks_from_prio(); + /* Initialize the interrupt related registers */ + for (i=0; i<3; i++) { + out_le32(BSP_irqCause_reg[i], 0); + out_le32(BSP_irqMask_reg[i], 0); + } + in_le32(BSP_irqMask_reg[2]); + compute_pic_masks_from_prio(); #if 0 - printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", - in_le32(BSP_irqMask_reg[0]), - in_le32(BSP_irqCause_reg[0])); - printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n", - in_le32(BSP_irqMask_reg[1]), - in_le32(BSP_irqCause_reg[1])); - printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n", - in_le32(BSP_irqMask_reg[2]), - in_le32(BSP_irqCause_reg[2])); + printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", + in_le32(BSP_irqMask_reg[0]), + in_le32(BSP_irqCause_reg[0])); + printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n", + in_le32(BSP_irqMask_reg[1]), + in_le32(BSP_irqCause_reg[1])); + printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n", + in_le32(BSP_irqMask_reg[2]), + in_le32(BSP_irqCause_reg[2])); #endif - /* - * - */ - for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) { - if ( BSP_config.irqHdlTbl[i].hdl != BSP_config.defaultEntry.hdl) { - BSP_enable_irq_at_pic(i); - BSP_config.irqHdlTbl[i].on(&BSP_config.irqHdlTbl[i]); - } - else { - BSP_config.irqHdlTbl[i].off(&BSP_config.irqHdlTbl[i]); - BSP_disable_irq_at_pic(i); - } - } - for (i= BSP_MAIN_GPP7_0_IRQ; i < BSP_MAIN_GPP31_24_IRQ; i++) + /* + * + */ + for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) { + if ( BSP_config.irqHdlTbl[i].hdl != BSP_config.defaultEntry.hdl) { BSP_enable_irq_at_pic(i); + BSP_config.irqHdlTbl[i].on(&BSP_config.irqHdlTbl[i]); + } + else { + BSP_config.irqHdlTbl[i].off(&BSP_config.irqHdlTbl[i]); + BSP_disable_irq_at_pic(i); + } + } + for (i= BSP_MAIN_GPP7_0_IRQ; i < BSP_MAIN_GPP31_24_IRQ; i++) + BSP_enable_irq_at_pic(i); - return(1); + return(1); } /* diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c index 96d9f36e05..d3ffa1e455 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c @@ -72,8 +72,6 @@ static rtems_pci_config_t BSP_pci[2]={ 0 /* defined at BSP_pci_configuration */} }; -extern void pci_interface(void); - /* Pack RegNum,FuncNum,DevNum,BusNum,and ConfigEnable for * PCI Configuration Address Register */ diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c b/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c index 493388a86b..9f3aceec21 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c @@ -15,16 +15,6 @@ static int BSP_pciDebug=0; -int BSP_pciFindDevicePrint(unsigned short vendorid, unsigned short deviceid, - int instance, int *pbus, int *pdev, int *pfun ) -{ - BSP_pciDebug = 1; - (void) pci_find_device(vendorid, deviceid, instance, pbus, pdev, pfun ); - BSP_pciDebug = 0; - - return 0; -} - int pci_find_device( unsigned short vendorid, unsigned short deviceid, int instance, int *pbus, int *pdev, int *pfun ) { @@ -33,37 +23,38 @@ int pci_find_device( unsigned short vendorid, unsigned short deviceid, unsigned char bus,dev,fun,hd; for (bus=0; bus= BSP_MAX_PCI_BUS_ON_PCI0)? 1:0, - (bus>= BSP_MAX_PCI_BUS_ON_PCI0)? bus-BSP_MAX_PCI_BUS_ON_PCI0:bus, - dev, fun); - } - - (void)pci_read_config_word(bus,dev,fun,PCI_VENDOR_ID,&s); - if (vendorid != s) - continue; - (void)pci_read_config_word(bus,dev,fun,PCI_DEVICE_ID,&s); - if (deviceid == s) { - if (instance--) continue; - *pbus=bus; *pdev=dev; *pfun=fun; - return 0; - } - } + for (dev=0; dev= BSP_MAX_PCI_BUS_ON_PCI0)? 1:0, + (bus>= BSP_MAX_PCI_BUS_ON_PCI0)? bus-BSP_MAX_PCI_BUS_ON_PCI0:bus, + dev, fun); + } + + (void)pci_read_config_word(bus,dev,fun,PCI_VENDOR_ID,&s); + if (vendorid != s) + continue; + (void)pci_read_config_word(bus,dev,fun,PCI_DEVICE_ID,&s); + if (deviceid == s) { + if (instance--) continue; + *pbus=bus; *pdev=dev; *pfun=fun; + return 0; + } } + } } /* end for bus */ return -1; } diff --git a/c/src/lib/libbsp/powerpc/mvme5500/startup/pgtbl_activate.c b/c/src/lib/libbsp/powerpc/mvme5500/startup/pgtbl_activate.c index 8145e2293a..79725c6a06 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/startup/pgtbl_activate.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/startup/pgtbl_activate.c @@ -1,8 +1,5 @@ -#include -#include -#include - -/* Default activation of the page tables. This is a weak +/* + * Default activation of the page tables. This is a weak * alias, so applications may easily override this * default activation procedure. */ @@ -11,25 +8,30 @@ * Kate Feng ported it to MVME5500, 4/2004 */ -void -BSP_pgtbl_activate(Triv121PgTbl) __attribute__ (( weak, alias("__BSP_default_pgtbl_activate") )); +#include +#include +#include -void +static void __BSP_default_pgtbl_activate(Triv121PgTbl pt) { - if (!pt) return; + if (!pt) + return; - /* switch the text/ro sements to RO only after - * initializing the interrupts because the irq_mng - * installs some code... - * - * activate the page table; it is still masked by the - * DBAT0, however - */ - triv121PgTblActivate(pt); + /* switch the text/ro sements to RO only after + * initializing the interrupts because the irq_mng + * installs some code... + * + * activate the page table; it is still masked by the + * DBAT0, however + */ + triv121PgTblActivate(pt); - /* finally, switch off DBAT0 & DBAT1 */ - setdbat(0,0,0,0,0); - setdbat(1,0,0,0,0); /* */ - /* At this point, DBAT0 is available for other use... */ + /* finally, switch off DBAT0 & DBAT1 */ + setdbat(0,0,0,0,0); + setdbat(1,0,0,0,0); /* */ + /* At this point, DBAT0 is available for other use... */ } + +void BSP_pgtbl_activate(Triv121PgTbl) + __attribute__ (( weak, alias("__BSP_default_pgtbl_activate") )); -- cgit v1.2.3