From 040ed0b4cdd1c663408664ba3a8b2e5de0cf54e0 Mon Sep 17 00:00:00 2001 From: Chris Nott Date: Sat, 18 Oct 2014 01:55:37 -0700 Subject: bsp/stm32f4: Add header files Added register definition headers for STM32F4 ADC, EXTI, PWR, SYSCFG, TIM, OTGFS and updated FLASH and RCC. Fixed PLL_Q for USB 48MHz operation. Added flash prefetch enable. --- c/src/lib/libbsp/arm/stm32f4/Makefile.am | 6 + c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 100 ++++- .../libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h | 64 +++ .../libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h | 111 +++-- .../libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h | 445 +++++++++++++++++++++ .../libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h | 47 +++ .../libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h | 146 ++++++- .../arm/stm32f4/include/stm32f4xxxx_syscfg.h | 108 +++++ .../libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h | 206 ++++++++++ c/src/lib/libbsp/arm/stm32f4/preinstall.am | 24 ++ c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c | 9 +- 11 files changed, 1209 insertions(+), 57 deletions(-) create mode 100644 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h mode change 100644 => 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h create mode 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h create mode 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h mode change 100644 => 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h create mode 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_syscfg.h create mode 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h diff --git a/c/src/lib/libbsp/arm/stm32f4/Makefile.am b/c/src/lib/libbsp/arm/stm32f4/Makefile.am index 055a0b1d1d..338f78de7f 100644 --- a/c/src/lib/libbsp/arm/stm32f4/Makefile.am +++ b/c/src/lib/libbsp/arm/stm32f4/Makefile.am @@ -49,9 +49,15 @@ include_bsp_HEADERS += include/stm32f4.h include_bsp_HEADERS += include/stm32f10xxx_gpio.h include_bsp_HEADERS += include/stm32f10xxx_rcc.h include_bsp_HEADERS += include/stm32f10xxx_exti.h +include_bsp_HEADERS += include/stm32f4xxxx_adc.h +include_bsp_HEADERS += include/stm32f4xxxx_exti.h include_bsp_HEADERS += include/stm32f4xxxx_gpio.h include_bsp_HEADERS += include/stm32f4xxxx_rcc.h +include_bsp_HEADERS += include/stm32f4xxxx_pwr.h +include_bsp_HEADERS += include/stm32f4xxxx_syscfg.h +include_bsp_HEADERS += include/stm32f4xxxx_tim.h include_bsp_HEADERS += include/stm32f4xxxx_flash.h +include_bsp_HEADERS += include/stm32f4xxxx_otgfs.h include_bsp_HEADERS += include/stm32_i2c.h include_bsp_HEADERS += include/i2c.h include_bsp_HEADERS += include/stm32_usart.h diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h index d26f914887..154d4f6d7b 100644 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h @@ -35,6 +35,11 @@ * @{ */ +#define STM32F4_APB1_BASE (STM32F4_BASE + 0x40000000) +#define STM32F4_APB2_BASE (STM32F4_BASE + 0x40010000) +#define STM32F4_AHB1_BASE (STM32F4_BASE + 0x40020000) +#define STM32F4_AHB2_BASE (STM32F4_BASE + 0x50000000) + /** * @name STM32f4XXXX GPIO * @{ @@ -51,7 +56,7 @@ */ #include -#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_BASE + 0x40023800)) +#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_AHB1_BASE + 0x3800)) /** @} */ @@ -93,6 +98,99 @@ /** @} */ +/** + * @name STM32f4XXXX PWR + * @{ + */ + +#include +#define STM32F4_PWR ((volatile stm32f4_pwr *) (STM32F4_APB1_BASE + 0x7000)) + +/** @} */ + +/** + * @name STM32f4XXXX EXTI + * @{ + */ + +#include +#define STM32F4_EXTI ((volatile stm32f4_exti *) (STM32F4_APB2_BASE + 0x3c00)) + +/** @} */ + +/** + * @name STM32f4XXXX SYSCFG + * @{ + */ + +#include +#define STM32F4_SYSCFG ((volatile stm32f4_syscfg *) (STM32F4_APB2_BASE + 0x3800)) + +/** @} */ + +/** + * @name STM32f4XXXX FLASH + * @{ + */ + +#include +#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_AHB1_BASE + 0x3c00)) + +/** @} */ + +/** + * @name STM32f4XXXX TIM + * @{ + */ + +#include +#define STM32F4_TIM1 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0000)) +#define STM32F4_TIM2 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0000)) +#define STM32F4_TIM3 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0400)) +#define STM32F4_TIM4 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0800)) +#define STM32F4_TIM5 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0c00)) +#define STM32F4_TIM6 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1000)) +#define STM32F4_TIM7 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1400)) +#define STM32F4_TIM8 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0400)) +#define STM32F4_TIM9 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4000)) +#define STM32F4_TIM10 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4400)) +#define STM32F4_TIM11 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4800)) +#define STM32F4_TIM12 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1800)) +#define STM32F4_TIM13 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1c00)) +#define STM32F4_TIM14 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x2000)) + +/** @} */ + +/** + * @name STM32f4XXXX ADC + * @{ + */ + +#include +#define STM32F4_ADC1 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2000)) +#define STM32F4_ADC2 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2100)) +#define STM32F4_ADC3 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2200)) +#define STM32F4_ADC_COMMON ((volatile stm32f4_adc_com *) (STM32F4_APB2_BASE + 0x2300)) + +/** @} */ + +/** + * @name STM32f4XXXX OTGFS + * @{ + */ + +#include +#define STM32F4_OTGFS_BASE (STM32F4_AHB2_BASE + 0x0000) +#define STM32F4_OTGFS_CORE ((volatile stm32f4_otgfs *) (STM32F4_OTGFS_BASE + 0x000)) +#define STM32F4_OTGFS_DEV ((volatile stm32f4_otgfs_dregs *) (STM32F4_OTGFS_BASE + 0x800)) +#define STM32F4_OTGFS_INEP ((volatile stm32f4_otgfs_inepregs *) (STM32F4_OTGFS_BASE + 0x900)) +#define STM32F4_OTGFS_OUTEP ((volatile stm32f4_otgfs_outepregs *) (STM32F4_OTGFS_BASE + 0xb00)) +#define STM32F4_OTGFS_PWRCTL ((volatile stm32f4_otgfs_pwrctlregs *) (STM32F4_OTGFS_BASE + 0xe00)) + +#define STM32F4_OTGFS_FIFO_BASE (STM32F4_OTGFS_BASE + USB_FIFO_BASE) + +/** @} */ + #endif /* STM32F4_FAMILY_F4XXXX */ #ifdef STM32F4_FAMILY_F10XXX diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h new file mode 100644 index 0000000000..feff2c6082 --- /dev/null +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H + +#include + +#define EXTI_PORTA 0 +#define EXTI_PORTB 1 +#define EXTI_PORTC 2 +#define EXTI_PORTD 3 +#define EXTI_PORTE 4 +#define EXTI_PORTF 5 +#define EXTI_PORTG 6 +#define EXTI_PORTH 7 +#define EXTI_PORTI 8 + +#define STM32F4_EXTI_LINE22 BSP_BIT32(21) +#define STM32F4_EXTI_LINE21 BSP_BIT32(21) +#define STM32F4_EXTI_LINE20 BSP_BIT32(20) +#define STM32F4_EXTI_LINE19 BSP_BIT32(19) +#define STM32F4_EXTI_LINE18 BSP_BIT32(18) +#define STM32F4_EXTI_LINE17 BSP_BIT32(17) +#define STM32F4_EXTI_LINE16 BSP_BIT32(16) +#define STM32F4_EXTI_LINE15 BSP_BIT32(15) +#define STM32F4_EXTI_LINE14 BSP_BIT32(14) +#define STM32F4_EXTI_LINE13 BSP_BIT32(13) +#define STM32F4_EXTI_LINE12 BSP_BIT32(12) +#define STM32F4_EXTI_LINE11 BSP_BIT32(11) +#define STM32F4_EXTI_LINE10 BSP_BIT32(10) +#define STM32F4_EXTI_LINE9 BSP_BIT32(9) +#define STM32F4_EXTI_LINE8 BSP_BIT32(8) +#define STM32F4_EXTI_LINE7 BSP_BIT32(7) +#define STM32F4_EXTI_LINE6 BSP_BIT32(6) +#define STM32F4_EXTI_LINE5 BSP_BIT32(5) +#define STM32F4_EXTI_LINE4 BSP_BIT32(4) +#define STM32F4_EXTI_LINE3 BSP_BIT32(3) +#define STM32F4_EXTI_LINE2 BSP_BIT32(2) +#define STM32F4_EXTI_LINE1 BSP_BIT32(1) +#define STM32F4_EXTI_LINE0 BSP_BIT32(0) + +struct stm32f4_exti_s { + uint32_t imr; // Interrupt mask + uint32_t emr; // Event mask + uint32_t rtsr; // Rising trigger selection + uint32_t ftsr; // Falling trigger selection + uint32_t swier; // Software interrupt event + uint32_t pr; // Pending +} __attribute__ ((packed)); +typedef struct stm32f4_exti_s stm32f4_exti; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h old mode 100644 new mode 100755 index 55d9dc6f3b..13f9045439 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h @@ -1,22 +1,15 @@ -/** - * @file - * - * @ingroup stm32f4_flash - * - * @brief STM32F4XXXX FLASH support. - * - * Contains structure desribing registers responsible for the flash memory - * configuration. - */ - /* - * Copyright (c) 2014 Tomasz Gregorek. All rights reserved. + * Copyright (c) 2013 Chris Nott. All rights reserved. * - * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * http://www.rtems.com/license/LICENSE. */ #ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H @@ -24,31 +17,67 @@ #include -/** - * @defgroup stm32f10xxx_flash STM32F4XXXX FLASH Support - * @ingroup stm32f4_flash - * @brief STM32F4FXXX FLASH Support - * @{ - */ +struct stm32f4_flash_s { + + uint32_t acr; // Access and control register +#define STM32F4_FLASH_ACR_DCRST BSP_BIT32(12) // Data cache reset +#define STM32F4_FLASH_ACR_ICRST BSP_BIT32(11) // Instruction cache reset +#define STM32F4_FLASH_ACR_DCEN BSP_BIT32(10) // Data cache enable +#define STM32F4_FLASH_ACR_ICEN BSP_BIT32(9) // Instruction cache enable +#define STM32F4_FLASH_ACR_PRFTEN BSP_BIT32(8) // Prefetch enable +#define STM32F4_FLASH_ACR_LATENCY(val) BSP_FLD32(val, 0, 2) // Flash access latency +#define STM32F4_FLASH_ACR_LATENCY_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define STM32F4_FLASH_ACR_LATENCY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + + uint32_t keyr; // Key register +#define STM32F4_FLASH_KEYR_KEY1 0x45670123 +#define STM32F4_FLASH_KEYR_KEY2 0xCDEF89AB + + uint32_t optkeyr; // Option key register +#define STM32F4_FLASH_OPTKEYR_OPTKEY1 0x08192A3B +#define STM32F4_FLASH_OPTKEYR_OPTKEY2 0x4C5D6E7F + + uint32_t sr; // Status register +#define STM32F4_FLASH_SR_BSY BSP_BIT32(16) // Busy +#define STM32F4_FLASH_SR_PGSERR BSP_BIT32(7) // Programming sequence error +#define STM32F4_FLASH_SR_PGPERR BSP_BIT32(6) // Programming parallelism error +#define STM32F4_FLASH_SR_PGAERR BSP_BIT32(5) // Programming alignment error +#define STM32F4_FLASH_SR_WRPERR BSP_BIT32(4) // Write protection error +#define STM32F4_FLASH_SR_OPERR BSP_BIT32(1) // Operation error +#define STM32F4_FLASH_SR_EOP BSP_BIT32(0) // End of operation + + uint32_t cr; // Control register +#define STM32F4_FLASH_CR_LOCK BSP_BIT32(31) // Lock +#define STM32F4_FLASH_CR_ERRIE BSP_BIT32(25) // Error interrupt enable +#define STM32F4_FLASH_CR_EOPIE BSP_BIT32(24) // End of operation interrupt enable +#define STM32F4_FLASH_CR_STRT BSP_BIT32(16) // Start +#define STM32F4_FLASH_CR_PSIZE(val) BSP_FLD32(val, 8, 9) // Program size +#define STM32F4_FLASH_CR_PSIZE_GET(reg) BSP_FLD32GET(reg, 8, 9) +#define STM32F4_FLASH_CR_PSIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) +#define STM32F4_FLASH_CR_SNB BSP_FLD32(val, 3, 6) // Sector number +#define STM32F4_FLASH_CR_SNB_GET(reg) BSP_FLD32GET(reg, 3, 6) +#define STM32F4_FLASH_CR_SNB_SET(reg, val) BSP_FLD32SET(reg, val, 3, 6) +#define STM32F4_FLASH_CR_MER BSP_BIT32(2) // Mass erase +#define STM32F4_FLASH_CR_SER BSP_BIT32(1) // Sector erase +#define STM32F4_FLASH_CR_PG BSP_BIT32(0) // Programming + + uint32_t optcr; // Option control register +#define STM32F4_FLASH_OPTCR_NWRP(val) BSP_FLD32(val, 16, 27) // Not write protect +#define STM32F4_FLASH_OPTCR_NWRP_GET(reg) BSP_FLD32GET(reg, 16, 27) +#define STM32F4_FLASH_OPTCR_NWRP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 27) +#define STM32F4_FLASH_OPTCR_RDP(val) BSP_FLD32(val, 8, 15) // Read protect +#define STM32F4_FLASH_OPTCR_RDP_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define STM32F4_FLASH_OPTCR_RDP_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define STM32F4_FLASH_OPTCR_USER(val) BSP_FLD32(val, 5, 7) // User option bytes +#define STM32F4_FLASH_OPTCR_USER_GET(reg) BSP_FLD32GET(reg, 5, 7) +#define STM32F4_FLASH_OPTCR_USER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) +#define STM32F4_FLASH_OPTCR_BOR_LEVEL(val) BSP_FLD32(val, 2, 3) // BOR reset level +#define STM32F4_FLASH_OPTCR_BOR_LEVEL_GET(reg) BSP_FLD32GET(reg, 2, 3) +#define STM32F4_FLASH_OPTCR_BOR_LEVEL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3) +#define STM32F4_FLASH_CR_OPTSTRT BSP_BIT32(1) // Option start +#define STM32F4_FLASH_CR_OPTLOCK BSP_BIT32(0) // Option lock + +} __attribute__ ((packed)); +typedef struct stm32f4_flash_s stm32f4_flash; -typedef struct { - uint32_t acr; - uint32_t keyr; - uint32_t optkeyr; - uint32_t sr; - uint32_t cr; - uint32_t optcr; - uint32_t optcr1; -} stm32f4_flash; - -/** @} */ - -#define FLASH_ACR_LATENCY( val ) BSP_FLD32( val, 0, 3 ) -#define FLASH_ACR_LATENCY_MSK BSP_MSK32( 0, 3 ) -#define FLASH_ACR_PRFTEN BSP_BIT32( 8 ) -#define FLASH_ACR_ICEN BSP_BIT32( 9 ) -#define FLASH_ACR_DCEN BSP_BIT32( 10 ) -#define FLASH_ACR_ICRST BSP_BIT32( 11 ) -#define FLASH_ACR_DCRST BSP_BIT32( 12 ) - -#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H */ \ No newline at end of file +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h new file mode 100755 index 0000000000..49beadc7af --- /dev/null +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H + +#include + +#define USB_OTG_NUM_EPS 4 +#define USB_OTG_MAX_TX_FIFOS 4 + +#define USB_FIFO_BASE 0x1000 +#define USB_FIFO_OFFS 0x1000 + +struct stm32f4_otgfs_s { + uint32_t gotgctl; // 0x00: Control and status register +#define STM32F4_OTGFS_GOTGCTL_BSVLD BSP_BIT32(19) // B-session valid +#define STM32F4_OTGFS_GOTGCTL_ASVLD BSP_BIT32(18) // A-session valid +#define STM32F4_OTGFS_GOTGCTL_DBCT BSP_BIT32(17) // Debounce time +#define STM32F4_OTGFS_GOTGCTL_CIDSTS BSP_BIT32(16) // Connector ID status +#define STM32F4_OTGFS_GOTGCTL_DHNPEN BSP_BIT32(11) // Device HNP enable +#define STM32F4_OTGFS_GOTGCTL_HSHNPEN BSP_BIT32(10) // Host set HNP enable +#define STM32F4_OTGFS_GOTGCTL_HNPRQ BSP_BIT32(9) // HNP request +#define STM32F4_OTGFS_GOTGCTL_HNGSCS BSP_BIT32(8) // Host negotiation status +#define STM32F4_OTGFS_GOTGCTL_SRQ BSP_BIT32(1) // Session request +#define STM32F4_OTGFS_GOTGCTL_SRQSCS BSP_BIT32(0) // Session request success + + uint32_t gotgint; // 0x04: Interrupt register +#define STM32F4_OTGFS_GOTGINT_DBCDNE BSP_BIT32(19) // Debounce done +#define STM32F4_OTGFS_GOTGINT_ADTOCHG BSP_BIT32(18) // A-device timeout change +#define STM32F4_OTGFS_GOTGINT_HNGDET BSP_BIT32(17) // Host negotiation detected +#define STM32F4_OTGFS_GOTGINT_HNSSCHG BSP_BIT32(9) // Host negotiation success status change +#define STM32F4_OTGFS_GOTGINT_SRSSCHG BSP_BIT32(8) // Session request status change +#define STM32F4_OTGFS_GOTGINT_SEDET BSP_BIT32(2) // Session end detected + + uint32_t gahbcfg; // 0x08: AHB configuration register +#define STM32F4_OTGFS_GAHBCFG_PTXFELVL BSP_BIT32(8) // Periodic txfifo empty level +#define STM32F4_OTGFS_GAHBCFG_TXFELVL BSP_BIT32(7) // Txfifo empty level +#define STM32F4_OTGFS_GAHBCFG_GINTMSK BSP_BIT32(0) // Global interrupt mask + + uint32_t gusbcfg; // 0x0C: USB configuration register +#define STM32F4_OTGFS_GUSBCFG_CTXPKT BSP_BIT32(31) // Corrupt TX packet +#define STM32F4_OTGFS_GUSBCFG_FDMOD BSP_BIT32(30) // Force device mode +#define STM32F4_OTGFS_GUSBCFG_FHMOD BSP_BIT32(29) // Force host mode +#define STM32F4_OTGFS_GUSBCFG_TRDT(val) BSP_FLD32(val, 10, 13) // USB turnaround time +#define STM32F4_OTGFS_GUSBCFG_TRDT_GET(reg) BSP_FLD32GET(reg, 10, 13) +#define STM32F4_OTGFS_GUSBCFG_TRDT_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13) +#define STM32F4_OTGFS_GUSBCFG_HNPCAP BSP_BIT32(9) // HNP-capable +#define STM32F4_OTGFS_GUSBCFG_SRPCAP BSP_BIT32(8) // SRP-capable +#define STM32F4_OTGFS_GUSBCFG_PHYSEL BSP_BIT32(6) // Full speed serial transceiver select +#define STM32F4_OTGFS_GUSBCFG_TOCAL(val) BSP_FLD32(val, 0, 2) // FS timeout calibration +#define STM32F4_OTGFS_GUSBCFG_TOCAL_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define STM32F4_OTGFS_GUSBCFG_TOCAL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + + uint32_t grstctl; // 0x10: Reset register +#define STM32F4_OTGFS_GRSTCTL_AHBIDL BSP_BIT32(31) // AHB master idle +#define STM32F4_OTGFS_GRSTCTL_TXFNUM(val) BSP_FLD32(val, 6, 10) // Tx fifo number +#define STM32F4_OTGFS_GRSTCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 6, 10) +#define STM32F4_OTGFS_GRSTCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10) +#define STM32F4_OTGFS_GRSTCTL_TXFNUM_ALL STM32F4_OTGFS_GRSTCTL_TXFNUM(0x10) +#define STM32F4_OTGFS_GRSTCTL_TXFFLSH BSP_BIT32(5) // TX fifo flush +#define STM32F4_OTGFS_GRSTCTL_RXFFLSH BSP_BIT32(4) // RX fifo flush +#define STM32F4_OTGFS_GRSTCTL_FCRST BSP_BIT32(2) // Host frame counter reset +#define STM32F4_OTGFS_GRSTCTL_HSRST BSP_BIT32(1) // HCLK soft reset +#define STM32F4_OTGFS_GRSTCTL_CSRST BSP_BIT32(0) // Core soft reset + + uint32_t gintsts; // 0x14: Core interrupt register +#define STM32F4_OTGFS_GINTSTS_WKUPINT BSP_BIT32(31) // Resume / remote wakeup detected interrupt +#define STM32F4_OTGFS_GINTSTS_SRQINT BSP_BIT32(30) // Session request / new session detected interrupt +#define STM32F4_OTGFS_GINTSTS_DISCINT BSP_BIT32(29) // Disconnect detected interrupt +#define STM32F4_OTGFS_GINTSTS_CIDSCHG BSP_BIT32(28) // Connector ID status change +#define STM32F4_OTGFS_GINTSTS_PTXFE BSP_BIT32(26) // Periodic TX fifo empty +#define STM32F4_OTGFS_GINTSTS_HCINT BSP_BIT32(25) // Host channels interrupt +#define STM32F4_OTGFS_GINTSTS_HPRTINT BSP_BIT32(24) // Host port interrupt +#define STM32F4_OTGFS_GINTSTS_IPXFR BSP_BIT32(21) // Incomplete periodic transfer +#define STM32F4_OTGFS_GINTSTS_IISOOXFR BSP_BIT32(21) // Incomplete isochronous OUT transfer +#define STM32F4_OTGFS_GINTSTS_IISOIXFR BSP_BIT32(20) // Incomplete isochronous IN transfer +#define STM32F4_OTGFS_GINTSTS_OEPINT BSP_BIT32(19) // OUT endpoint interrupt +#define STM32F4_OTGFS_GINTSTS_IEPINT BSP_BIT32(18) // IN endpoint interrupt +#define STM32F4_OTGFS_GINTSTS_EOPF BSP_BIT32(15) // End of periodic frame interrupt +#define STM32F4_OTGFS_GINTSTS_ISOODRP BSP_BIT32(14) // Isochronous OUT packet dropped interrupt +#define STM32F4_OTGFS_GINTSTS_ENUMDNE BSP_BIT32(13) // Enumeration done +#define STM32F4_OTGFS_GINTSTS_USBRST BSP_BIT32(12) // USB reset +#define STM32F4_OTGFS_GINTSTS_USBSUSP BSP_BIT32(11) // USB suspend +#define STM32F4_OTGFS_GINTSTS_ESUSP BSP_BIT32(10) // Early suspend +#define STM32F4_OTGFS_GINTSTS_GONAKEFF BSP_BIT32(7) // Global OUT NAK effective +#define STM32F4_OTGFS_GINTSTS_GINAKEFF BSP_BIT32(6) // Global IN non-periodic NAK effective +#define STM32F4_OTGFS_GINTSTS_NPTXFE BSP_BIT32(5) // Non-periodic TX fifo empty +#define STM32F4_OTGFS_GINTSTS_RXFLVL BSP_BIT32(4) // RX fifo non-empty +#define STM32F4_OTGFS_GINTSTS_SOF BSP_BIT32(3) // Start of frame +#define STM32F4_OTGFS_GINTSTS_OTGINT BSP_BIT32(2) // OTG interrupt +#define STM32F4_OTGFS_GINTSTS_MMIS BSP_BIT32(1) // Mode mismatch interrupt +#define STM32F4_OTGFS_GINTSTS_CMOD BSP_BIT32(0) // Current mode of operation + + uint32_t gintmsk; // 0x18: Interrupt mask register + + uint32_t grxstsr; // 0x1C: Receive status debug read + + uint32_t grxstsp; // 0x20: OTG status read and pop +#define STM32F4_OTGFS_GRXSTSP_FRMNUM(val) BSP_FLD32(val, 21, 24) // Frame number +#define STM32F4_OTGFS_GRXSTSP_FRMNUM_GET(reg) BSP_FLD32GET(reg, 21, 24) +#define STM32F4_OTGFS_GRXSTSP_FRMNUM_SET(reg, val) BSP_FLD32SET(reg, val, 21, 24) +#define STM32F4_OTGFS_GRXSTSP_PKTSTS(val) BSP_FLD32(val, 17, 20) // Packet status +#define STM32F4_OTGFS_GRXSTSP_PKTSTS_GET(reg) BSP_FLD32GET(reg, 17, 20) +#define STM32F4_OTGFS_GRXSTSP_PKTSTS_SET(reg, val) BSP_FLD32SET(reg, val, 17, 20) +#define PKTSTS_IN_DATA (0x2) +#define PKTSTS_IN_COMPLETE (0x3) +#define PKTSTS_TOGGLE_ERR (0x5) +#define PKTSTS_HALTED (0x7) +#define PKTSTS_OUTNAK (0x1) +#define PKTSTS_OUT_DATA (0x2) +#define PKTSTS_OUT_COMPLETE (0x3) +#define PKTSTS_SETUP_COMPLETE (0x4) +#define PKTSTS_SETUP_DATA (0x6) +#define STM32F4_OTGFS_GRXSTSP_DPIG(val) BSP_FLD32(val, 15, 16) // Data PID +#define STM32F4_OTGFS_GRXSTSP_DPID_GET(reg) BSP_FLD32GET(reg, 15, 16) +#define STM32F4_OTGFS_GRXSTSP_DPID_SET(reg, val) BSP_FLD32SET(reg, val, 15, 16) +#define STM32F4_OTGFS_GRXSTSP_DPID_DATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x0) +#define STM32F4_OTGFS_GRXSTSP_DPID_DATA1 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x1) +#define STM32F4_OTGFS_GRXSTSP_DPID_DATA2 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x2) +#define STM32F4_OTGFS_GRXSTSP_DPID_MDATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x3) +#define STM32F4_OTGFS_GRXSTSP_BCNT(val) BSP_FLD32(val, 4, 14) // Byte count +#define STM32F4_OTGFS_GRXSTSP_BCNT_GET(reg) BSP_FLD32GET(reg, 4, 14) +#define STM32F4_OTGFS_GRXSTSP_BCNT_SET(reg, val) BSP_FLD32SET(reg, val, 4, 14) +#define STM32F4_OTGFS_GRXSTSP_CHNUM(val) BSP_FLD32(val, 0, 3) // Channel number +#define STM32F4_OTGFS_GRXSTSP_CHNUM_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_OTGFS_GRXSTSP_CHNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_OTGFS_GRXSTSP_EPNUM(val) BSP_FLD32(val, 0, 3) // Endpoint number +#define STM32F4_OTGFS_GRXSTSP_EPNUM_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_OTGFS_GRXSTSP_EPNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + + uint32_t grxfsiz; // 0x24: Receive FIFO size register +#define STM32F4_OTGFS_GRXFSIZ_RXFD(val) BSP_FLD32(val, 0, 15) +#define STM32F4_OTGFS_GRXFSIZ_RXFD_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_GRXFSIZ_RXFD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) +#define STM32F4_OTGFS_GRXFSIZ_RXFD_MIN 16 +#define STM32F4_OTGFS_GRXFSIZ_RXFD_MAX 256 + + uint32_t dieptxf0; // 0x28: EP 0 transmit fifo size +#define STM32F4_OTGFS_DIEPTXF_DEPTH(val) BSP_FLD32(val, 16, 31) +#define STM32F4_OTGFS_DIEPTXF_DEPTH_GET(reg) BSP_FLD32GET(reg, 16, 31) +#define STM32F4_OTGFS_DIEPTXF_DEPTH_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) +#define STM32F4_OTGFS_DIEPTXF_DEPTH_MIN 16 +#define STM32F4_OTGFS_DIEPTXF_DEPTH_MAX 256 +#define STM32F4_OTGFS_DIEPTXF_SADDR(val) BSP_FLD32(val, 0, 15) +#define STM32F4_OTGFS_DIEPTXF_SADDR_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DIEPTXF_SADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t resv2C; + + uint32_t gi2cctl; // 0x30 + uint32_t resv34; // 0x34 + + uint32_t gccfg; // 0x38: General core configuration register +#define STM32F4_OTGFS_GCCFG_NOVBUSSENS BSP_BIT32(21) // Vbus sensing disable +#define STM32F4_OTGFS_GCCFG_SOFOUTEN BSP_BIT32(20) // SOF output enable +#define STM32F4_OTGFS_GCCFG_VBUSBSEN BSP_BIT32(19) // Vbus sensing "B" device +#define STM32F4_OTGFS_GCCFG_VBUSASEN BSP_BIT32(18) // Vbus sensing "A" device +#define STM32F4_OTGFS_GCCFG_PWRDWN BSP_BIT32(16) // Power down + + uint32_t cid; // 0x3C: Product ID + + uint32_t resv40[48]; // 0x40 - 0x9C + + uint32_t hptxfsiz; // 0x100 + + uint32_t dieptxf[USB_OTG_MAX_TX_FIFOS]; // 0x104 + +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_s stm32f4_otgfs; + +struct stm32f4_otgfs_dregs_s { + uint32_t dcfg; // 0x800 +#define STM32F4_OTGFS_DCFG_PFIVL(val) BSP_FLD32(val, 11, 12) // Periodic frame interval +#define STM32F4_OTGFS_DCFG_PFIVL_GET(reg) BSP_FLD32GET(reg, 11, 12) +#define STM32F4_OTGFS_DCFG_PFIVL_SET(reg, val) BSP_FLD32SET(reg, val, 11, 12) +#define PFIVL_80 0 +#define PFIVL_85 1 +#define PFIVL_90 2 +#define PFIVL_95 3 +#define STM32F4_OTGFS_DCFG_DAD(val) BSP_FLD32(val, 4, 10) // Device address +#define STM32F4_OTGFS_DCFG_DAD_GET(reg) BSP_FLD32GET(reg, 4, 10) +#define STM32F4_OTGFS_DCFG_DAD_SET(reg, val) BSP_FLD32SET(reg, val, 4, 10) +#define STM32F4_OTGFS_DCFG_NZLSOHSK BSP_BIT32(2) // Non-zero-length status OUT handshake +#define STM32F4_OTGFS_DCFG_DSPD(val) BSP_FLD32(val, 0, 1) // Device speed +#define STM32F4_OTGFS_DCFG_DSPD_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_OTGFS_DCFG_DSPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define STM32F4_OTGFS_DCFG_DSPD_FULL STM32F4_OTGFS_DCFG_DSPD(0x3) + + uint32_t dctl; // 0x804 +#define STM32F4_OTGFS_DCTL_POPRGDNE BSP_BIT32(11) // Power-on programming done +#define STM32F4_OTGFS_DCTL_CGONAK BSP_BIT32(10) // Clear global OUT NAK +#define STM32F4_OTGFS_DCTL_SGONAK BSP_BIT32(9) // Set global OUT NAK +#define STM32F4_OTGFS_DCTL_CGINAK BSP_BIT32(8) // Clear global IN NAK +#define STM32F4_OTGFS_DCTL_SGINAK BSP_BIT32(7) // Set global IN NAK +#define STM32F4_OTGFS_DCTL_TCTL(val) BSP_FLD32(val, 4, 6) // Test control +#define STM32F4_OTGFS_DCTL_TCTL_GET(reg) BSP_FLD32GET(reg, 4, 6) +#define STM32F4_OTGFS_DCTL_TCTL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 6) +#define STM32F4_OTGFS_DCTL_GONSTS BSP_BIT32(3) // Global OUT NAK status +#define STM32F4_OTGFS_DCTL_GINSTS BSP_BIT32(2) // Global IN NAK status +#define STM32F4_OTGFS_DCTL_SDIS BSP_BIT32(1) // Soft disconnect +#define STM32F4_OTGFS_DCTL_RWUSIG BSP_BIT32(0) // Remote wakeup signalling + + uint32_t dsts; // 0x808 +#define STM32F4_OTGFS_DSTS_FNSOF(val) BSP_FLD32(val, 8, 21) // Frame number of received SOF +#define STM32F4_OTGFS_DSTS_FNSOF_GET(reg) BSP_FLD32GET(reg, 8, 21) +#define STM32F4_OTGFS_DSTS_EERR BSP_BIT32(3) // Erratic error +#define STM32F4_OTGFS_DSTS_ENUMSPD(val) BSP_FLD32(val, 1, 2) // Enumerated speed +#define STM32F4_OTGFS_DSTS_ENUMSPD_GET(reg) BSP_FLD32GET(reg, 1, 2) +#define STM32F4_OTGFS_DSTS_ENUMSPD_FULL STM32F4_OTGFS_DSTS_ENUMSPD(0x3) +#define STM32F4_OTGFS_DSTS_SUSPSTS BSP_BIT32(0) // Suspend status + + uint32_t unused4; // 0x80C + + uint32_t diepmsk; // 0x810 + + uint32_t doepmsk; // 0x814 + + uint32_t daint; // 0x818 +#define STM32F4_OTGFS_DAINT_OEPINT15 BSP_BIT32(31) // OUT endpoint 15 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT14 BSP_BIT32(30) // OUT endpoint 14 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT13 BSP_BIT32(29) // OUT endpoint 13 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT12 BSP_BIT32(28) // OUT endpoint 12 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT11 BSP_BIT32(27) // OUT endpoint 11 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT10 BSP_BIT32(26) // OUT endpoint 10 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT9 BSP_BIT32(25) // OUT endpoint 9 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT8 BSP_BIT32(24) // OUT endpoint 8 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT7 BSP_BIT32(23) // OUT endpoint 7 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT6 BSP_BIT32(22) // OUT endpoint 6 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT5 BSP_BIT32(21) // OUT endpoint 5 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT4 BSP_BIT32(20) // OUT endpoint 4 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT3 BSP_BIT32(19) // OUT endpoint 3 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT2 BSP_BIT32(18) // OUT endpoint 2 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT1 BSP_BIT32(17) // OUT endpoint 1 interrupt +#define STM32F4_OTGFS_DAINT_OEPINT0 BSP_BIT32(16) // OUT endpoint 0 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT15 BSP_BIT32(15) // IN endpoint 15 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT14 BSP_BIT32(14) // IN endpoint 14 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT13 BSP_BIT32(13) // IN endpoint 13 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT12 BSP_BIT32(12) // IN endpoint 12 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT11 BSP_BIT32(11) // IN endpoint 11 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT10 BSP_BIT32(10) // IN endpoint 10 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT9 BSP_BIT32(9) // IN endpoint 9 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT8 BSP_BIT32(8) // IN endpoint 8 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT7 BSP_BIT32(7) // IN endpoint 7 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT6 BSP_BIT32(6) // IN endpoint 6 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT5 BSP_BIT32(5) // IN endpoint 5 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT4 BSP_BIT32(4) // IN endpoint 4 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT3 BSP_BIT32(3) // IN endpoint 3 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT2 BSP_BIT32(2) // IN endpoint 2 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT1 BSP_BIT32(1) // IN endpoint 1 interrupt +#define STM32F4_OTGFS_DAINT_IEPINT0 BSP_BIT32(0) // IN endpoint 0 interrupt + + uint32_t daintmsk; // 0x81C +#define STM32F4_OTGFS_DAINTMSK_OEPM(val) BSP_FLD32(val, 16, 31) // OUT endpoint interrupt mask +#define STM32F4_OTGFS_DAINTMSK_OEPM_GET(reg) BSP_FLD32GET(reg, 16, 31) +#define STM32F4_OTGFS_DAINTMSK_OEPM_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) +#define STM32F4_OTGFS_DAINTMSK_IEPM(val) BSP_FLD32(val, 0, 15) // IN endpoint interrupt mask +#define STM32F4_OTGFS_DAINTMSK_IEPM_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DAINTMSK_IEPM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t unused5[2]; // 0x820 - 0x824 + + uint32_t dvbusdis; // 0x828 +#define STM32F4_OTGFS_DVBUSDIS_VBUSDT(val) BSP_FLD32(val, 0, 15) // Device Vbus discharge time +#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t dvbuspulse; // 0x82C +#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP(val) BSP_FLD32(val, 0, 15) // Device Vbus pulsing time +#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t unused6; // 0x830 + + uint32_t diepempmsk; // 0x834 +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM15 BSP_BIT32(15) // IN endpoint 15 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM14 BSP_BIT32(14) // IN endpoint 14 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM13 BSP_BIT32(13) // IN endpoint 13 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM12 BSP_BIT32(12) // IN endpoint 12 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM11 BSP_BIT32(11) // IN endpoint 11 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM10 BSP_BIT32(10) // IN endpoint 10 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM9 BSP_BIT32(9) // IN endpoint 9 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM8 BSP_BIT32(8) // IN endpoint 8 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM7 BSP_BIT32(7) // IN endpoint 7 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM6 BSP_BIT32(6) // IN endpoint 6 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM5 BSP_BIT32(5) // IN endpoint 5 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM4 BSP_BIT32(4) // IN endpoint 4 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM3 BSP_BIT32(3) // IN endpoint 3 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM2 BSP_BIT32(2) // IN endpoint 2 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM1 BSP_BIT32(1) // IN endpoint 1 TxFIFO empty interrupt mask +#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM0 BSP_BIT32(0) // IN endpoint 0 TxFIFO empty interrupt mask + +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_dregs_s stm32f4_otgfs_dregs; + +struct stm32f4_otgfs_inepregs_s { + uint32_t diepctl; // 0x900 +#define STM32F4_OTGFS_DIEPCTL_EPENA BSP_BIT32(31) // Endpoint enable +#define STM32F4_OTGFS_DIEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable +#define STM32F4_OTGFS_DIEPCTL_SODDFRM BSP_BIT32(29) // Set odd frame +#define STM32F4_OTGFS_DIEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame +#define STM32F4_OTGFS_DIEPCTL_SEVNFRM BSP_BIT32(28) // Set DATA0 PID / Set even frame +#define STM32F4_OTGFS_DIEPCTL_SNAK BSP_BIT32(27) // Set NAK +#define STM32F4_OTGFS_DIEPCTL_CNAK BSP_BIT32(26) // Clear NAK +#define STM32F4_OTGFS_DIEPCTL_TXFNUM(val) BSP_FLD32(val, 22, 25) // TxFIFO number +#define STM32F4_OTGFS_DIEPCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 22, 25) +#define STM32F4_OTGFS_DIEPCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 22, 25) +#define STM32F4_OTGFS_DIEPCTL_STALL BSP_BIT32(21) // Stall handshake +#define STM32F4_OTGFS_DIEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt +#define STM32F4_OTGFS_DIEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19) +#define STM32F4_OTGFS_DIEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) +#define EPTYPE_CTRL 0 +#define EPTYPE_ISOC 1 +#define EPTYPE_BULK 2 +#define EPTYPE_INTR 3 +#define STM32F4_OTGFS_DIEPCTL_NAKSTS BSP_BIT32(17) // NAK status +#define STM32F4_OTGFS_DIEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame +#define STM32F4_OTGFS_DIEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ(val) BSP_FLD32(val, 0, 1) // Maximum packet size (bytes) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define EP0_MPSIZ_8 3 +#define EP0_MPSIZ_16 2 +#define EP0_MPSIZ_32 1 +#define EP0_MPSIZ_64 0 +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_8 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_8) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_16 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_16) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_32 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_32) +#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_64 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_64) +#define STM32F4_OTGFS_DIEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes) +#define STM32F4_OTGFS_DIEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10) +#define STM32F4_OTGFS_DIEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10) + + uint32_t reserved_04; + + uint32_t diepint; // 0x908 +#define STM32F4_OTGFS_DIEPINT_TXFE BSP_BIT32(7) // Transmit FIFO empty +#define STM32F4_OTGFS_DIEPINT_INEPNE BSP_BIT32(6) // IN endpoint NAK effective +#define STM32F4_OTGFS_DIEPINT_ITTXFE BSP_BIT32(4) // IN token received, TxFIFO empty +#define STM32F4_OTGFS_DIEPINT_TOC BSP_BIT32(3) // Timeout condition +#define STM32F4_OTGFS_DIEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled +#define STM32F4_OTGFS_DIEPINT_XFRC BSP_BIT32(0) // Transfer complete + + uint32_t reserved_0C; + + uint32_t dieptsiz; // 0x910 +#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT(val) BSP_FLD32(val, 19, 20) // EP0 packet count +#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 20) +#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 20) +#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size +#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) +#define STM32F4_OTGFS_DIEPTSIZ_MCNT(val) BSP_FLD32(val, 29, 30) // Multi count +#define STM32F4_OTGFS_DIEPTSIZ_MCNT_GET(reg) BSP_FLD32GET(reg, 29, 30) +#define STM32F4_OTGFS_DIEPTSIZ_MCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) +#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count +#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28) +#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28) +#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size +#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18) +#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18) + + uint32_t reserved_14; + + uint32_t dtxfsts; // 0x918 +#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV(val) BSP_FLD32(val, 0, 15) // IN endpoint TxFIFO space available +#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_GET(reg) BSP_FLD32(reg, 0, 15) +#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + + uint32_t reserved_1C; + +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_inepregs_s stm32f4_otgfs_inepregs; + +struct stm32f4_otgfs_outepregs_s { + uint32_t doepctl; // 0xBx0: Endpoint control register +#define STM32F4_OTGFS_DOEPCTL_EPENA BSP_BIT32(31) // Endpoint enable +#define STM32F4_OTGFS_DOEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable +#define STM32F4_OTGFS_DOEPCTL_SD1PID BSP_BIT32(29) // Set DATA1 PID / Set odd frame +#define STM32F4_OTGFS_DOEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame +#define STM32F4_OTGFS_DOEPCTL_SNAK BSP_BIT32(27) // Set NAK +#define STM32F4_OTGFS_DOEPCTL_CNAK BSP_BIT32(26) // Clear NAK +#define STM32F4_OTGFS_DOEPCTL_STALL BSP_BIT32(21) // Stall handshake +#define STM32F4_OTGFS_DOEPCTL_SNPM BSP_BIT32(20) // Snoop mode +#define STM32F4_OTGFS_DOEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt +#define STM32F4_OTGFS_DOEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19) +#define STM32F4_OTGFS_DOEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) +#define STM32F4_OTGFS_DOEPCTL_NAKSTS BSP_BIT32(17) // NAK status +#define STM32F4_OTGFS_DOEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame +#define STM32F4_OTGFS_DOEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint +#define STM32F4_OTGFS_DOEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes) +#define STM32F4_OTGFS_DOEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10) +#define STM32F4_OTGFS_DOEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10) + + uint32_t resv04; + + uint32_t doepint; // 0xBx8: Endpoint interrupt register +#define STM32F4_OTGFS_DOEPINT_B2BSTUP BSP_BIT32(6) // Back-to-back SETUP packets received +#define STM32F4_OTGFS_DOEPINT_OTEPDIS BSP_BIT32(4) // OUT token received when endpoint disabled +#define STM32F4_OTGFS_DOEPINT_STUP BSP_BIT32(3) // SETUP phase done +#define STM32F4_OTGFS_DOEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled interrupt +#define STM32F4_OTGFS_DOEPINT_XFRC BSP_BIT32(0) // Transfer complete + + uint32_t doeptsiz; // 0xBy0 +#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT(val) BSP_FLD32(val, 29, 30) // EP0 SETUP packet count +#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_GET(reg) BSP_FLD32GET(reg, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_EP0_PKTCNT BSP_BIT32(19) // EP0 packet count +#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size +#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6) +#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) +#define STM32F4_OTGFS_DOEPTSIZ_RXDPID(val) BSP_FLD32(val, 29, 30) // Received data PID +#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_GET(reg) BSP_FLD32GET(reg, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) +#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count +#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28) +#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28) +#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size +#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18) +#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18) + + uint32_t resv14[3]; +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_outepregs_s stm32f4_otgfs_outepregs; + +struct stm32f4_otgfs_pwrctlregs_s { + uint32_t pcgcctl; // 0xE00: Power and clock gating control register +#define STM32F4_OTGFS_PCGCCTL_PHYSUSP BSP_BIT32(4) // PHY suspend +#define STM32F4_OTGFS_PCGCCTL_GATEHCLK BSP_BIT32(1) // Gate HCLK +#define STM32F4_OTGFS_PCGCCTL_STPPCLK BSP_BIT32(0) // Stop PHY clk +} __attribute__ ((packed)); +typedef struct stm32f4_otgfs_pwrctlregs_s stm32f4_otgfs_pwrctlregs; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h new file mode 100755 index 0000000000..48ed66ddc6 --- /dev/null +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H + +#include + +struct stm32f4_pwr_s { + + uint32_t cr; // Control register +#define STM32F4_PWR_CR_VOS BSP_BIT32(14) // Regulator scaling output selection +#define STM32F4_PWR_CR_FPDS BSP_BIT32(9) // Flash power-down in stop mode +#define STM32F4_PWR_CR_DBP BSP_BIT32(8) // Disable backup domain write protection +#define STM32F4_PWR_CR_PLS BSP_FLD32(val, 5, 7) // PVD level selection +#define STM32F4_PWR_CR_PLS_GET(reg) BSP_FLD32GET(reg, 5, 7) +#define STM32F4_PWR_CR_PLS_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) +#define STM32F4_PWR_CR_PVDE BSP_BIT32(4) // Power voltage detector enable +#define STM32F4_PWR_CR_CSBF BSP_BIT32(3) // Clear standby flag +#define STM32F4_PWR_CR_CWUF BSP_BIT32(2) // Clear wakeup flag +#define STM32F4_PWR_CR_PDDS BSP_BIT32(1) // Power-down deepsleep +#define STM32F4_PWR_CR_LPDS BSP_BIT32(0) // Low-power deepsleep + + uint32_t csr; // Control / status register +#define STM32F4_PWR_CSR_VOSRDY BSP_BIT32(14) // Regulator voltage scaling output selection ready bit +#define STM32F4_PWR_CSR_BRE BSP_BIT32(9) // Backup domain regulator enable +#define STM32F4_PWR_CSR_EWUP BSP_BIT32(8) // Enable WKUP pin +#define STM32F4_PWR_CSR_BRR BSP_BIT32(3) // Backup regulator ready +#define STM32F4_PWR_CSR_PVDO BSP_BIT32(2) // PVD output +#define STM32F4_PWR_CSR_SBF BSP_BIT32(1) // Standby flag +#define STM32F4_PWR_CSR_WUF BSP_BIT32(0) // Wakeup flag + +} __attribute__ ((packed)); +typedef struct stm32f4_pwr_s stm32f4_pwr; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h old mode 100644 new mode 100755 index 311e484235..5c004328d7 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h @@ -32,26 +32,150 @@ typedef struct { uint32_t cr; +#define STM32F4_RCC_CR_PLLI2SRDY BSP_BIT32(27) // PLLI2S clock ready flag +#define STM32F4_RCC_CR_PLLI2SON BSP_BIT32(26) // PLLI2S enable +#define STM32F4_RCC_CR_PLLRDY BSP_BIT32(25) // Main PLL clock ready flag +#define STM32F4_RCC_CR_PLLON BSP_BIT32(24) // Main PLL enable +#define STM32F4_RCC_CR_CSSON BSP_BIT32(19) // Clock security system enable +#define STM32F4_RCC_CR_HSEBYP BSP_BIT32(18) // HSE clock bypass +#define STM32F4_RCC_CR_HSERDY BSP_BIT32(17) // HSE clock ready flag +#define STM32F4_RCC_CR_HSEON BSP_BIT32(16) // HSE clock enable +#define STM32F4_RCC_CR_HSIRDY BSP_BIT32(1) // HSI clock ready flag +#define STM32F4_RCC_CR_HSION BSP_BIT32(0) // HSI clock enable + uint32_t pllcfgr; +#define STM32F4_RCC_PLLCFGR_PLLQ(val) BSP_FLD32(val, 24, 27) +#define STM32F4_RCC_PLLCFGR_PLLQ_GET(reg) BSP_FLD32GET(reg, 24, 27) +#define STM32F4_RCC_PLLCFGR_PLLQ_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27) +#define STM32F4_RCC_PLLCFGR_SRC BSP_BIT32(22) // PLL entry clock source +#define STM32F4_RCC_PLLCFGR_SRC_HSE STM32F4_RCC_PLLCFGR_SRC +#define STM32F4_RCC_PLLCFGR_SRC_HSI 0 +#define STM32F4_RCC_PLLCFGR_PLLP(val) BSP_FLD32(val, 16, 17) +#define STM32F4_RCC_PLLCFGR_PLLP_GET(reg) BSP_FLD32GET(reg, 16, 17) +#define STM32F4_RCC_PLLCFGR_PLLP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) +#define STM32F4_RCC_PLLCFGR_PLLP_2 STM32F4_RCC_PLLCFGR_PLLP(0) +#define STM32F4_RCC_PLLCFGR_PLLP_4 STM32F4_RCC_PLLCFGR_PLLP(1) +#define STM32F4_RCC_PLLCFGR_PLLP_6 STM32F4_RCC_PLLCFGR_PLLP(2) +#define STM32F4_RCC_PLLCFGR_PLLP_8 STM32F4_RCC_PLLCFGR_PLLP(3) +#define STM32F4_RCC_PLLCFGR_PLLN(val) BSP_FLD32(val, 6, 14) +#define STM32F4_RCC_PLLCFGR_PLLN_GET(reg) BSP_FLD32GET(reg, 6, 14) +#define STM32F4_RCC_PLLCFGR_PLLN_SET(reg, val) BSP_FLD32SET(reg, val, 6, 14) +#define STM32F4_RCC_PLLCFGR_PLLM(val) BSP_FLD32(val, 0, 5) +#define STM32F4_RCC_PLLCFGR_PLLM_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define STM32F4_RCC_PLLCFGR_PLLM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t cfgr; +#define STM32F4_RCC_CFGR_MCO2(val) BSP_FLD32(val, 30, 31) // Microcontroller clock output 2 +#define STM32F4_RCC_CFGR_MCO2_GET(reg) BSP_FLD32GET(reg, 30, 31) +#define STM32F4_RCC_CFGR_MCO2_SET(reg, val) BSP_FLD32SET(reg, val, 30, 31) +#define STM32F4_RCC_CFGR_MCO2_SYSCLK STM32F4_RCC_CFGR_MCO2(0) +#define STM32F4_RCC_CFGR_MCO2_PLLI2S STM32F4_RCC_CFGR_MCO2(1) +#define STM32F4_RCC_CFGR_MCO2_HSE STM32F4_RCC_CFGR_MCO2(2) +#define STM32F4_RCC_CFGR_MCO2_PLL STM32F4_RCC_CFGR_MCO2(3) +#define STM32F4_RCC_CFGR_MCO2_PRE(val) BSP_FLD32(val, 27, 29) // MCO2 prescalar +#define STM32F4_RCC_CFGR_MCO2_PRE_GET(reg) BSP_FLD32GET(reg, 27, 29) +#define STM32F4_RCC_CFGR_MCO2_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29) +#define STM32F4_RCC_CFGR_MCO2_DIV1 STM32F4_RCC_CFGR_MCO2_PRE(0) +#define STM32F4_RCC_CFGR_MCO2_DIV2 STM32F4_RCC_CFGR_MCO2_PRE(4) +#define STM32F4_RCC_CFGR_MCO2_DIV3 STM32F4_RCC_CFGR_MCO2_PRE(5) +#define STM32F4_RCC_CFGR_MCO2_DIV4 STM32F4_RCC_CFGR_MCO2_PRE(6) +#define STM32F4_RCC_CFGR_MCO2_DIV5 STM32F4_RCC_CFGR_MCO2_PRE(7) +#define STM32F4_RCC_CFGR_MCO1_PRE(val) BSP_FLD32(val, 24, 26) // MCO1 prescalar +#define STM32F4_RCC_CFGR_MCO1_PRE_GET(reg) BSP_FLD32GET(reg, 24, 26) +#define STM32F4_RCC_CFGR_MCO1_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) +#define STM32F4_RCC_CFGR_MCO1_DIV1 STM32F4_RCC_CFGR_MCO1_PRE(0) +#define STM32F4_RCC_CFGR_MCO1_DIV2 STM32F4_RCC_CFGR_MCO1_PRE(4) +#define STM32F4_RCC_CFGR_MCO1_DIV3 STM32F4_RCC_CFGR_MCO1_PRE(5) +#define STM32F4_RCC_CFGR_MCO1_DIV4 STM32F4_RCC_CFGR_MCO1_PRE(6) +#define STM32F4_RCC_CFGR_MCO1_DIV5 STM32F4_RCC_CFGR_MCO1_PRE(7) +#define STM32F4_RCC_CFGR_I2SSCR BSP_BIT32(23) // I2S clock selection +#define STM32F4_RCC_CFGR_MCO1(val) BSP_FLD32(val, 21, 22) // Microcontroller clock output 1 +#define STM32F4_RCC_CFGR_MCO1_GET(reg) BSP_FLD32GET(reg, 21, 22) +#define STM32F4_RCC_CFGR_MCO1_SET(reg, val) BSP_FLD32SET(reg, val, 21, 22) +#define STM32F4_RCC_CFGR_MCO1_HSI STM32F4_RCC_CFGR_MCO1(0) +#define STM32F4_RCC_CFGR_MCO1_LSE STM32F4_RCC_CFGR_MCO1(1) +#define STM32F4_RCC_CFGR_MCO1_HSE STM32F4_RCC_CFGR_MCO1(2) +#define STM32F4_RCC_CFGR_MCO1_PLL STM32F4_RCC_CFGR_MCO1(3) +#define STM32F4_RCC_CFGR_RTCPRE(val) BSP_FLD32(val, 16, 20) // HSE division factor for RTC clock +#define STM32F4_RCC_CFGR_RTCPRE_GET(reg) BSP_FLD32GET(reg, 16, 20) +#define STM32F4_RCC_CFGR_RTCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20) +#define STM32F4_RCC_CFGR_PPRE2(val) BSP_FLD32(val, 13, 15) // APB high-speed prescalar (APB2) +#define STM32F4_RCC_CFGR_PPRE2_GET(reg) BSP_FLD32GET(reg, 13, 15) +#define STM32F4_RCC_CFGR_PPRE2_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15) +#define STM32F4_RCC_CFGR_PPRE2_DIV1 STM32F4_RCC_CFGR_PPRE2(0) +#define STM32F4_RCC_CFGR_PPRE2_DIV2 STM32F4_RCC_CFGR_PPRE2(4) +#define STM32F4_RCC_CFGR_PPRE2_DIV4 STM32F4_RCC_CFGR_PPRE2(5) +#define STM32F4_RCC_CFGR_PPRE2_DIV8 STM32F4_RCC_CFGR_PPRE2(6) +#define STM32F4_RCC_CFGR_PPRE2_DIV16 STM32F4_RCC_CFGR_PPRE2(7) +#define STM32F4_RCC_CFGR_PPRE1(val) BSP_FLD32(val, 10, 12) // APB low-speed prescalar (APB1) +#define STM32F4_RCC_CFGR_PPRE1_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define STM32F4_RCC_CFGR_PPRE1_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define STM32F4_RCC_CFGR_PPRE1_DIV1 STM32F4_RCC_CFGR_PPRE1(0) +#define STM32F4_RCC_CFGR_PPRE1_DIV2 STM32F4_RCC_CFGR_PPRE1(4) +#define STM32F4_RCC_CFGR_PPRE1_DIV4 STM32F4_RCC_CFGR_PPRE1(5) +#define STM32F4_RCC_CFGR_PPRE1_DIV8 STM32F4_RCC_CFGR_PPRE1(6) +#define STM32F4_RCC_CFGR_PPRE1_DIV16 STM32F4_RCC_CFGR_PPRE1(7) +#define STM32F4_RCC_CFGR_HPRE(val) BSP_FLD32(val, 4, 15) // AHB prescalar +#define STM32F4_RCC_CFGR_HPRE_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_RCC_CFGR_HPRE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_RCC_CFGR_HPRE_DIV1 STM32F4_RCC_CFGR_HPRE(0) +#define STM32F4_RCC_CFGR_HPRE_DIV2 STM32F4_RCC_CFGR_HPRE(8) +#define STM32F4_RCC_CFGR_HPRE_DIV4 STM32F4_RCC_CFGR_HPRE(9) +#define STM32F4_RCC_CFGR_HPRE_DIV8 STM32F4_RCC_CFGR_HPRE(10) +#define STM32F4_RCC_CFGR_HPRE_DIV16 STM32F4_RCC_CFGR_HPRE(11) +#define STM32F4_RCC_CFGR_HPRE_DIV64 STM32F4_RCC_CFGR_HPRE(12) +#define STM32F4_RCC_CFGR_HPRE_DIV128 STM32F4_RCC_CFGR_HPRE(13) +#define STM32F4_RCC_CFGR_HPRE_DIV256 STM32F4_RCC_CFGR_HPRE(14) +#define STM32F4_RCC_CFGR_HPRE_DIV512 STM32F4_RCC_CFGR_HPRE(15) +#define STM32F4_RCC_CFGR_SWS(val) BSP_FLD32(val, 2, 3) // System clock switch status +#define STM32F4_RCC_CFGR_SWS_GET(reg) BSP_FLD32GET(reg, 2, 3) +#define STM32F4_RCC_CFGR_SWS_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3) +#define STM32F4_RCC_CFGR_SWS_HSI STM32F4_RCC_CFGR_SWS(0) +#define STM32F4_RCC_CFGR_SWS_HSE STM32F4_RCC_CFGR_SWS(1) +#define STM32F4_RCC_CFGR_SWS_PLL STM32F4_RCC_CFGR_SWS(2) +#define STM32F4_RCC_CFGR_SW(val) BSP_FLD32(val, 0, 1) // System clock switch +#define STM32F4_RCC_CFGR_SW_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_RCC_CFGR_SW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define STM32F4_RCC_CFGR_SW_HSI STM32F4_RCC_CFGR_SW(0) +#define STM32F4_RCC_CFGR_SW_HSE STM32F4_RCC_CFGR_SW(1) +#define STM32F4_RCC_CFGR_SW_PLL STM32F4_RCC_CFGR_SW(2) + uint32_t cir; - uint32_t ahbrstr[ 3 ]; + + uint32_t ahbrstr [3]; + uint32_t reserved_1c; - uint32_t apbrstr[ 2 ]; - uint32_t reserved_28[ 2 ]; - uint32_t ahbenr[ 3 ]; + + uint32_t apbrstr [2]; + + uint32_t reserved_28 [2]; + + uint32_t ahbenr [3]; + uint32_t reserved_3c; - uint32_t apbenr[ 2 ]; - uint32_t reserved_48[ 2 ]; - uint32_t ahblpenr[ 3 ]; + + uint32_t apbenr [2]; + + uint32_t reserved_48 [2]; + + uint32_t ahblpenr [3]; + uint32_t reserved_5c; - uint32_t apblpenr[ 2 ]; - uint32_t reserved_68[ 2 ]; + + uint32_t apblpenr [2]; + + uint32_t reserved_68 [2]; + uint32_t bdcr; + uint32_t csr; - uint32_t reserved_78[ 2 ]; + + uint32_t reserved_78 [2]; + uint32_t sscgr; + uint32_t plli2scfgr; + } stm32f4_rcc; /** @} */ @@ -162,4 +286,4 @@ typedef struct { #define RCC_CFGR_MCO2_HSE BSP_FLD32( 2, 30, 31 ) #define RCC_CFGR_MCO2_PLL BSP_FLD32( 3, 30, 31 ) -#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */ \ No newline at end of file +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_syscfg.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_syscfg.h new file mode 100755 index 0000000000..f7e81db639 --- /dev/null +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_syscfg.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H + +#include + +#define EXTI_PORTA 0 +#define EXTI_PORTB 1 +#define EXTI_PORTC 2 +#define EXTI_PORTD 3 +#define EXTI_PORTE 4 +#define EXTI_PORTF 5 +#define EXTI_PORTG 6 +#define EXTI_PORTH 7 +#define EXTI_PORTI 8 + +struct stm32f4_syscfg_s { + uint32_t memrmp; // Memory remap +#define STM32F4_SYSCFG_MEM_MODE(val) BSP_FLD32(val, 0, 1) +#define STM32F4_SYSCFG_MEM_MODE_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define STM32F4_SYSCFG_MEM_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) + uint32_t pmc; // Peripheral mode configuration +#define STM32F4_SYSCFG_RMII_SEL BSP_BIT32(23) + uint32_t exticr[4]; // External interrupt configuration +#define STM32F4_SYSCFG_EXTI0_IDX 0 +#define STM32F4_SYSCFG_EXTI0(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI0_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI1_IDX 0 +#define STM32F4_SYSCFG_EXTI1(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI1_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI2_IDX 0 +#define STM32F4_SYSCFG_EXTI2(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI2_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI3_IDX 0 +#define STM32F4_SYSCFG_EXTI3(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI3_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define STM32F4_SYSCFG_EXTI4_IDX 1 +#define STM32F4_SYSCFG_EXTI4(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI4_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI4_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI5_IDX 1 +#define STM32F4_SYSCFG_EXTI5(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI5_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI5_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI6_IDX 1 +#define STM32F4_SYSCFG_EXTI6(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI6_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI6_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI7_IDX 1 +#define STM32F4_SYSCFG_EXTI7(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI7_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI7_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define STM32F4_SYSCFG_EXTI8_IDX 2 +#define STM32F4_SYSCFG_EXTI8(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI8_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI8_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI9_IDX 2 +#define STM32F4_SYSCFG_EXTI9(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI9_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI9_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI10_IDX 2 +#define STM32F4_SYSCFG_EXTI10(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI10_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI10_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI11_IDX 2 +#define STM32F4_SYSCFG_EXTI11(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI11_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI11_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define STM32F4_SYSCFG_EXTI12_IDX 3 +#define STM32F4_SYSCFG_EXTI12(val) BSP_FLD32(val, 0, 3) +#define STM32F4_SYSCFG_EXTI12_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_SYSCFG_EXTI12_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define STM32F4_SYSCFG_EXTI13_IDX 3 +#define STM32F4_SYSCFG_EXTI13(val) BSP_FLD32(val, 4, 7) +#define STM32F4_SYSCFG_EXTI13_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define STM32F4_SYSCFG_EXTI13_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define STM32F4_SYSCFG_EXTI14_IDX 3 +#define STM32F4_SYSCFG_EXTI14(val) BSP_FLD32(val, 8, 11) +#define STM32F4_SYSCFG_EXTI14_GET(reg) BSP_FLD32GET(reg, 8, 11) +#define STM32F4_SYSCFG_EXTI14_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define STM32F4_SYSCFG_EXTI15_IDX 3 +#define STM32F4_SYSCFG_EXTI15(val) BSP_FLD32(val, 12, 15) +#define STM32F4_SYSCFG_EXTI15_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define STM32F4_SYSCFG_EXTI15_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) + uint32_t cmpcr; // Compensation cell control register +#define STM32F4_SYSCFG_CMPCR_READY BSP_BIT32(8) +#define STM32F4_SYSCFG_CMPCR_PD BSP_BIT32(0) +} __attribute__ ((packed)); +typedef struct stm32f4_syscfg_s stm32f4_syscfg; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h new file mode 100755 index 0000000000..c7317ebf41 --- /dev/null +++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2013 Chris Nott. All rights reserved. + * + * Virtual Logic + * 21-25 King St. + * Rockdale NSW 2216 + * Australia + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H +#define LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H + +#include + +struct stm32f4_tim_s { + uint16_t cr1; // Control register 1 +#define STM32F4_TIMER_CR1_CKD_DIV 0x0300 +#define STM32F4_TIMER_CR1_CKD_DIV1 0x0000 +#define STM32F4_TIMER_CR1_CKD_DIV2 0x0100 +#define STM32F4_TIMER_CR1_CKD_DIV3 0x0200 +#define STM32F4_TIMER_CR1_ARPE BSP_BIT16(7) +#define STM32F4_TIMER_CR1_CMS 0x0060 +#define STM32F4_TIMER_CR1_CMS_EDGE 0x0000 +#define STM32F4_TIMER_CR1_CMS_CENTER1 0x0020 +#define STM32F4_TIMER_CR1_CMS_CENTER2 0x0040 +#define STM32F4_TIMER_CR1_CMS_CENTER3 0x0060 +#define STM32F4_TIMER_CR1_DIR BSP_BIT16(4) +#define STM32F4_TIMER_CR1_DIR_UP 0x0000 +#define STM32F4_TIMER_CR1_DIR_DOWN 0x0010 +#define STM32F4_TIMER_CR1_DIR_OPM 0x0008 +#define STM32F4_TIMER_CR1_DIR_OPM_CONT 0x0000 +#define STM32F4_TIMER_CR1_DIR_OPM_STOP 0x0008 +#define STM32F4_TIMER_CR1_DIR_URS 0x0004 +#define STM32F4_TIMER_CR1_DIR_UDIS 0x0002 +#define STM32F4_TIMER_CR1_DIR_UDIS_EN 0x0000 +#define STM32F4_TIMER_CR1_DIR_UDIS_DIS 0x0002 +#define STM32F4_TIMER_CR1_CEN 0x0001 + uint16_t reserved_02; + uint16_t cr2; // Control register 2 + uint16_t reserved_06; + uint16_t smcr; // Slave mode control register + uint16_t reserved_0a; + uint16_t dier; // DMA / interrupt enable register +#define STM32F4_TIMER_DIER_TDE BSP_BIT16(14) // Trigger DMA request enable +#define STM32F4_TIMER_DIER_CC4DE BSP_BIT16(12) // Capture/compare 4 DMA request enable +#define STM32F4_TIMER_DIER_CC3DE BSP_BIT16(11) // Capture/compare 3 DMA request enable +#define STM32F4_TIMER_DIER_CC2DE BSP_BIT16(10) // Capture/compare 2 DMA request enable +#define STM32F4_TIMER_DIER_CC1DE BSP_BIT16(9) // Capture/compare 1 DMA request enable +#define STM32F4_TIMER_DIER_UDE BSP_BIT16(8) // Update DMA request enable +#define STM32F4_TIMER_DIER_TIE BSP_BIT16(6) // Trigger interrupt enable +#define STM32F4_TIMER_DIER_CC4IE BSP_BIT16(4) // Capture/compare 4 interrupt request enable +#define STM32F4_TIMER_DIER_CC3IE BSP_BIT16(3) // Capture/compare 3 interrupt request enable +#define STM32F4_TIMER_DIER_CC2IE BSP_BIT16(2) // Capture/compare 2 interrupt request enable +#define STM32F4_TIMER_DIER_CC1IE BSP_BIT16(1) // Capture/compare 1 interrupt request enable +#define STM32F4_TIMER_DIER_UIE BSP_BIT16(0) // Update interrupt request enable + + uint16_t reserved_0e; + uint16_t sr; // Status register +#define STM32F4_TIMER_SR_CC4OF BSP_BIT16(12) // Capture/compare 4 overcapture flag +#define STM32F4_TIMER_SR_CC3OF BSP_BIT16(11) // Capture/compare 3 overcapture flag +#define STM32F4_TIMER_SR_CC2OF BSP_BIT16(10) // Capture/compare 2 overcapture flag +#define STM32F4_TIMER_SR_CC1OF BSP_BIT16(9) // Capture/compare 1 overcapture flag +#define STM32F4_TIMER_SR_TIF BSP_BIT16(6) // Trigger interrupt flag +#define STM32F4_TIMER_SR_CC4IF BSP_BIT16(4) // Capture/compare 4 interrupt flag +#define STM32F4_TIMER_SR_CC3IF BSP_BIT16(3) // Capture/compare 3 interrupt flag +#define STM32F4_TIMER_SR_CC2IF BSP_BIT16(2) // Capture/compare 2 interrupt flag +#define STM32F4_TIMER_SR_CC1IF BSP_BIT16(1) // Capture/compare 1 interrupt flag +#define STM32F4_TIMER_SR_UIF BSP_BIT16(0) // Update interrupt flag + uint16_t reserved_12; + uint16_t egr; // Event generation register +#define STM32F4_TIMER_EGR_TG BSP_BIT16(6) // Trigger event +#define STM32F4_TIMER_EGR_CC4G BSP_BIT16(4) // Capture/compare 4 event +#define STM32F4_TIMER_EGR_CC3G BSP_BIT16(3) // Capture/compare 3 generation) +#define STM32F4_TIMER_EGR_CC2G BSP_BIT16(2) // Capture/compare 2 generation) +#define STM32F4_TIMER_EGR_CC1G BSP_BIT16(1) // Capture/compare 1 generation) +#define STM32F4_TIMER_EGR_UG BSP_BIT16(0) // Update event + uint16_t reserved_16; + uint16_t ccmr1; // Capture / compare mode register 1 +#define STM32F4_TIMER_CCMR1_OC2CE BSP_BIT16(15) // Output compare 2 clear enable +#define STM32F4_TIMER_CCMR1_OC2M(val) BSP_FLD16(val, 12, 14) +#define STM32F4_TIMER_CCMR1_OC2M_GET(reg) BSP_FLD16GET(reg, 12, 14) +#define STM32F4_TIMER_CCMR1_OC2M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14) +#define STM32F4_TIMER_CCMR1_OC2M_FROZEN STM32F4_TIMER_CCMR1_OC2M(0) +#define STM32F4_TIMER_CCMR1_OC2M_ACTIVE STM32F4_TIMER_CCMR1_OC2M(1) +#define STM32F4_TIMER_CCMR1_OC2M_INACTIVE STM32F4_TIMER_CCMR1_OC2M(2) +#define STM32F4_TIMER_CCMR1_OC2M_TOGGLE STM32F4_TIMER_CCMR1_OC2M(3) +#define STM32F4_TIMER_CCMR1_OC2M_FORCE_LOW STM32F4_TIMER_CCMR1_OC2M(4) +#define STM32F4_TIMER_CCMR1_OC2M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC2M(5) +#define STM32F4_TIMER_CCMR1_OC2M_PWM1 STM32F4_TIMER_CCMR1_OC2M(6) +#define STM32F4_TIMER_CCMR1_OC2M_PWM2 STM32F4_TIMER_CCMR1_OC2M(7) +#define STM32F4_TIMER_CCMR1_OC2PE BSP_BIT16(11) // Output compare 2 preload enable +#define STM32F4_TIMER_CCMR1_OC2FE BSP_BIT16(10) // Output compare 2 fast enable +#define STM32F4_TIMER_CCMR1_CC2S(val) BSP_FLD16(val, 8, 9) +#define STM32F4_TIMER_CCMR1_CC2S_GET(reg) BSP_FLD16GET(reg, 8, 9) +#define STM32F4_TIMER_CCMR1_CC2S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9) +#define STM32F4_TIMER_CCMR1_CC2S_OUTPUT STM32F4_TIMER_CCMR1_OC2S(0) +#define STM32F4_TIMER_CCMR1_CC2S_TI2 STM32F4_TIMER_CCMR1_OC2S(1) +#define STM32F4_TIMER_CCMR1_CC2S_TI1 STM32F4_TIMER_CCMR1_OC2S(2) +#define STM32F4_TIMER_CCMR1_CC2S_TRC STM32F4_TIMER_CCMR1_OC2S(3) +#define STM32F4_TIMER_CCMR1_OC1CE BSP_BIT16(7) // Output compare 1 clear enable +#define STM32F4_TIMER_CCMR1_OC1M(val) BSP_FLD16(val, 4, 6) +#define STM32F4_TIMER_CCMR1_OC1M_GET(reg) BSP_FLD16GET(reg, 4, 6) +#define STM32F4_TIMER_CCMR1_OC1M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6) +#define STM32F4_TIMER_CCMR1_OC1M_FROZEN STM32F4_TIMER_CCMR1_OC1M(0) +#define STM32F4_TIMER_CCMR1_OC1M_ACTIVE STM32F4_TIMER_CCMR1_OC1M(1) +#define STM32F4_TIMER_CCMR1_OC1M_INACTIVE STM32F4_TIMER_CCMR1_OC1M(2) +#define STM32F4_TIMER_CCMR1_OC1M_TOGGLE STM32F4_TIMER_CCMR1_OC1M(3) +#define STM32F4_TIMER_CCMR1_OC1M_FORCE_LOW STM32F4_TIMER_CCMR1_OC1M(4) +#define STM32F4_TIMER_CCMR1_OC1M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC1M(5) +#define STM32F4_TIMER_CCMR1_OC1M_PWM1 STM32F4_TIMER_CCMR1_OC1M(6) +#define STM32F4_TIMER_CCMR1_OC1M_PWM2 STM32F4_TIMER_CCMR1_OC1M(7) +#define STM32F4_TIMER_CCMR1_OC1PE BSP_BIT16(3) // Output compare 1 preload enable +#define STM32F4_TIMER_CCMR1_OC1FE BSP_BIT16(2) // Output compare 1 fast enable +#define STM32F4_TIMER_CCMR1_CC1S(val) BSP_FLD16(val, 0, 1) +#define STM32F4_TIMER_CCMR1_CC1S_GET(reg) BSP_FLD16GET(reg, 0, 1) +#define STM32F4_TIMER_CCMR1_CC1S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1) +#define STM32F4_TIMER_CCMR1_CC1S_OUTPUT STM32F4_TIMER_CCMR1_OC1S(0) +#define STM32F4_TIMER_CCMR1_CC1S_TI2 STM32F4_TIMER_CCMR1_OC1S(1) +#define STM32F4_TIMER_CCMR1_CC1S_TI1 STM32F4_TIMER_CCMR1_OC1S(2) +#define STM32F4_TIMER_CCMR1_CC1S_TRC STM32F4_TIMER_CCMR1_OC1S(3) + uint16_t reserved_1a; + uint16_t ccmr2; // Capture / compare mode register 2 +#define STM32F4_TIMER_CCMR2_OC4CE BSP_BIT16(15) // Output compare 4 clear enable +#define STM32F4_TIMER_CCMR2_OC4M(val) BSP_FLD16(val, 12, 14) +#define STM32F4_TIMER_CCMR2_OC4M_GET(reg) BSP_FLD16GET(reg, 12, 14) +#define STM32F4_TIMER_CCMR2_OC4M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14) +#define STM32F4_TIMER_CCMR2_OC4M_FROZEN STM32F4_TIMER_CCMR2_OC4M(0) +#define STM32F4_TIMER_CCMR2_OC4M_ACTIVE STM32F4_TIMER_CCMR2_OC4M(1) +#define STM32F4_TIMER_CCMR2_OC4M_INACTIVE STM32F4_TIMER_CCMR2_OC4M(2) +#define STM32F4_TIMER_CCMR2_OC4M_TOGGLE STM32F4_TIMER_CCMR2_OC4M(3) +#define STM32F4_TIMER_CCMR2_OC4M_FORCE_LOW STM32F4_TIMER_CCMR2_OC4M(4) +#define STM32F4_TIMER_CCMR2_OC4M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC4M(5) +#define STM32F4_TIMER_CCMR2_OC4M_PWM1 STM32F4_TIMER_CCMR2_OC4M(6) +#define STM32F4_TIMER_CCMR2_OC4M_PWM2 STM32F4_TIMER_CCMR2_OC4M(7) +#define STM32F4_TIMER_CCMR2_OC4PE BSP_BIT16(11) // Output compare 4 preload enable +#define STM32F4_TIMER_CCMR2_OC4FE BSP_BIT16(10) // Output compare 4 fast enable +#define STM32F4_TIMER_CCMR2_CC4S(val) BSP_FLD16(val, 8, 9) +#define STM32F4_TIMER_CCMR2_CC4S_GET(reg) BSP_FLD16GET(reg, 8, 9) +#define STM32F4_TIMER_CCMR2_CC4S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9) +#define STM32F4_TIMER_CCMR2_CC4S_OUTPUT STM32F4_TIMER_CCMR2_OC4S(0) +#define STM32F4_TIMER_CCMR2_CC4S_TI2 STM32F4_TIMER_CCMR2_OC4S(1) +#define STM32F4_TIMER_CCMR2_CC4S_TI1 STM32F4_TIMER_CCMR2_OC4S(2) +#define STM32F4_TIMER_CCMR2_CC4S_TRC STM32F4_TIMER_CCMR2_OC4S(3) +#define STM32F4_TIMER_CCMR2_OC3CE BSP_BIT16(7) // Output compare 3 clear enable +#define STM32F4_TIMER_CCMR2_OC3M(val) BSP_FLD16(val, 4, 6) +#define STM32F4_TIMER_CCMR2_OC3M_GET(reg) BSP_FLD16GET(reg, 4, 6) +#define STM32F4_TIMER_CCMR2_OC3M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6) +#define STM32F4_TIMER_CCMR2_OC3M_FROZEN STM32F4_TIMER_CCMR2_OC3M(0) +#define STM32F4_TIMER_CCMR2_OC3M_ACTIVE STM32F4_TIMER_CCMR2_OC3M(1) +#define STM32F4_TIMER_CCMR2_OC3M_INACTIVE STM32F4_TIMER_CCMR2_OC3M(2) +#define STM32F4_TIMER_CCMR2_OC3M_TOGGLE STM32F4_TIMER_CCMR2_OC3M(3) +#define STM32F4_TIMER_CCMR2_OC3M_FORCE_LOW STM32F4_TIMER_CCMR2_OC3M(4) +#define STM32F4_TIMER_CCMR2_OC3M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC3M(5) +#define STM32F4_TIMER_CCMR2_OC3M_PWM1 STM32F4_TIMER_CCMR2_OC3M(6) +#define STM32F4_TIMER_CCMR2_OC3M_PWM2 STM32F4_TIMER_CCMR2_OC3M(7) +#define STM32F4_TIMER_CCMR2_OC3PE BSP_BIT16(3) // Output compare 3 preload enable +#define STM32F4_TIMER_CCMR2_OC3FE BSP_BIT16(2) // Output compare 3 fast enable +#define STM32F4_TIMER_CCMR2_CC3S(val) BSP_FLD16(val, 0, 1) +#define STM32F4_TIMER_CCMR2_CC3S_GET(reg) BSP_FLD16GET(reg, 0, 1) +#define STM32F4_TIMER_CCMR2_CC3S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1) +#define STM32F4_TIMER_CCMR2_CC3S_OUTPUT STM32F4_TIMER_CCMR2_OC3S(0) +#define STM32F4_TIMER_CCMR2_CC3S_TI2 STM32F4_TIMER_CCMR2_OC3S(1) +#define STM32F4_TIMER_CCMR2_CC3S_TI1 STM32F4_TIMER_CCMR2_OC3S(2) +#define STM32F4_TIMER_CCMR2_CC3S_TRC STM32F4_TIMER_CCMR2_OC3S(3) + uint16_t reserved_1e; + uint16_t ccer; // Capture / compare enable register +#define STM32F4_TIMER_CCER_CC4NP BSP_BIT16(15) // Capture / compare 4 output polarity +#define STM32F4_TIMER_CCER_CC4P BSP_BIT16(13) // Capture / compare 4 output polarity +#define STM32F4_TIMER_CCER_CC4E BSP_BIT16(12) // Capture / compare 4 output enable +#define STM32F4_TIMER_CCER_CC3NP BSP_BIT16(11) // Capture / compare 3 output polarity +#define STM32F4_TIMER_CCER_CC3P BSP_BIT16(9) // Capture / compare 3 output polarity +#define STM32F4_TIMER_CCER_CC3E BSP_BIT16(8) // Capture / compare 3 output enable +#define STM32F4_TIMER_CCER_CC2NP BSP_BIT16(7) // Capture / compare 2 output polarity +#define STM32F4_TIMER_CCER_CC2P BSP_BIT16(5) // Capture / compare 2 output polarity +#define STM32F4_TIMER_CCER_CC2E BSP_BIT16(4) // Capture / compare 2 output enable +#define STM32F4_TIMER_CCER_CC1NP BSP_BIT16(3) // Capture / compare 1 output polarity +#define STM32F4_TIMER_CCER_CC1P BSP_BIT16(1) // Capture / compare 1 output polarity +#define STM32F4_TIMER_CCER_CC1E BSP_BIT16(0) // Capture / compare 1 output enable + uint16_t reserved_22; + uint32_t cnt; // Counter register +#define STM32F4_TIMER_DR(val) BSP_FLD32(val, 0, 31) +#define STM32F4_TIMER_DR_GET(reg) BSP_FLD32GET(reg, 0, 31) +#define STM32F4_TIMER_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31) + uint16_t psc; // Prescalar + uint16_t reserved_2a; + uint32_t arr; // Auto-reload register + uint16_t rcr; // Repetition counter register + uint16_t rserved_32; + uint32_t ccr[4];// Capture / compare registers + uint16_t bdtr; // Break and dead-time register + uint16_t reserved_46; + uint16_t dcr; // DMA control register + uint16_t reserved_4a; + uint16_t dmar; // DMA address for full transfer + uint16_t reserved_4e; + uint16_t or; // Option register + uint16_t reserved_52; +} __attribute__ ((packed)); +typedef struct stm32f4_tim_s stm32f4_tim; + +#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/preinstall.am b/c/src/lib/libbsp/arm/stm32f4/preinstall.am index fe9a3b073a..ce390f3d45 100644 --- a/c/src/lib/libbsp/arm/stm32f4/preinstall.am +++ b/c/src/lib/libbsp/arm/stm32f4/preinstall.am @@ -113,6 +113,14 @@ $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h: include/stm32f10xxx_exti.h $(PROJECT_ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h +$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h: include/stm32f4xxxx_adc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h + +$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h: include/stm32f4xxxx_exti.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h + $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h: include/stm32f4xxxx_gpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h @@ -121,10 +129,26 @@ $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h: include/stm32f4xxxx_rcc.h $(PROJECT_IN $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h +$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h: include/stm32f4xxxx_pwr.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h + +$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h: include/stm32f4xxxx_syscfg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h + +$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h: include/stm32f4xxxx_tim.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h + $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h: include/stm32f4xxxx_flash.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h +$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h: include/stm32f4xxxx_otgfs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h + $(PROJECT_INCLUDE)/bsp/stm32_i2c.h: include/stm32_i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32_i2c.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32_i2c.h diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c b/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c index 0d08458c2e..8d4bf6b82b 100644 --- a/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c +++ b/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c @@ -174,7 +174,7 @@ static rtems_status_code set_system_clk( /* pll_q is a prescaler from VCO for the USB OTG FS, SDIO and RNG, * best if results in the 48MHz for the USB */ - pll_q = ( (long) ( src_clk * pll_n + src_clk * pll_n / 2 ) ) / pll_m / 48; + pll_q = ( (long) ( src_clk * pll_n ) ) / pll_m / 48; if ( pll_q < 2 ) { pll_q = 2; @@ -257,9 +257,10 @@ static rtems_status_code set_system_clk( * Set flash parameters, hard coded for now for fast system clocks. * TODO implement some math to use flash on as low latancy as possible */ - flash->acr = FLASH_ACR_LATENCY( 5 ) | /* latency */ - FLASH_ACR_ICEN | /* instruction cache */ - FLASH_ACR_DCEN; /* data cache */ + flash->acr = STM32F4_FLASH_ACR_LATENCY( 5 ) | /* latency */ + STM32F4_FLASH_ACR_ICEN | /* instruction cache */ + STM32F4_FLASH_ACR_DCEN | /* data cache */ + STM32F4_FLASH_ACR_PRFTEN; /* turn on PLL */ rcc->cr |= RCC_CR_PLLON; -- cgit v1.2.3