summaryrefslogtreecommitdiffstats
path: root/c (follow)
Commit message (Collapse)AuthorAgeFilesLines
* bsps/sparc: Fix copy of initialized dataSebastian Huber2016-11-022-7/+8
| | | | | The text and data sections may have different alignment requirements. Support a data section alignment greater than 16.
* Updated xilinx_zynq_a9_qemu bsp README instructions.James2016-10-251-2/+2
|
* bsps/sparc: Add interrupt controller registersSebastian Huber2016-10-191-2/+5
|
* bsp/leon3: Avoid implicit integer conversionsSebastian Huber2016-10-191-8/+8
|
* atsam: multiple messages on one cs low levelAlexander Krutwig2016-10-172-8/+14
|
* libchip/network/if_fxp.c: do not use rtems_interrupt_disable.Pavel Pisa2016-10-171-7/+4
| | | | | | | | | | The single write to memory or ioport output are mostly atomic operations already. The proper memory synchronization barrier should be used around them to guarantee ordering (sync or eieio on PowerPC for example) but because I have not found settable portable primitive only compiler barrier is used. It should be enough on x86 because the externally visible order should be/is guaranteed to be preserved on x86 architecture.
* bsps/i386: use Pentimum instructions for pc586 and pc686 builds.Pavel Pisa2016-10-172-2/+2
| | | | | | | | | | | | | | | | | | When GCC option -march is not specifies i386-rtems toolchain defaults to i386 architecture instruction set. It does not provide atomic instructions which results in really inefficient atomic_fetch_or even on UP build. SMP build is broken with i386 set because libatomic and GCC generate infinite loop for __atomic_fetch_add_4 used in rtems_interrupt_lock_acquire __atomic_fetch_add_4: push %ebp mov %esp,%ebp movl $0x5,0x10(%ebp) pop %ebp jmp __atomic_fetch_add_4
* bsps/i386: replace global interrupt disable by SMP build supporting locking.Pavel Pisa2016-10-179-72/+148
|
* bsp/atsamv: Fix typoSebastian Huber2016-10-131-1/+1
|
* bsps/i386: Separate variable for i8259 IRQs disable due to in progress state.Pavel Pisa2016-10-111-19/+36
| | | | | | | | The global state of enabled and disabled interrupts has to hold interrupts really disabled by drivers and system. If the state is combined with interrupts temporarily disabled because they are processed at given time then it is impossible to maintain state by interrupt handlers in drivers.
* bsp/qoriq: Add GPIO register mapSebastian Huber2016-10-111-1/+14
|
* bsps/sparc: Support GR740 GPIOSebastian Huber2016-10-111-0/+22
|
* bsp/atsam: Provide default buffer countsSebastian Huber2016-10-051-2/+11
|
* bsp/atsam: Fix PHY detectionSebastian Huber2016-10-051-16/+11
|
* bsp/mvme147*: Fix linker issueSebastian Huber2016-09-232-6/+2
| | | | | The GNU linker does not allow a nonconstant expression for a region length.
* bsps/m68k: Add libatomic support to some bsp_specsSebastian Huber2016-09-233-3/+3
| | | | Update #2695.
* bsps/m68k: Fix linker command fileSebastian Huber2016-09-231-1/+1
| | | | Prevent garbage collection of interrupt vector table.
* arm/tms570: document BSP setup with included hardware initialization.Pavel Pisa2016-09-221-22/+100
|
* arm/tms570: update bootstrap generated preinstall.amPavel Pisa2016-09-221-0/+13
|
* arm/tms570: include TMS570_USE_HWINIT_STARTUP option to select bare metal ↵Pavel Pisa2016-09-222-0/+26
| | | | startup and selftest.
* arm/tms570: include hardware initialization and selftest based on Ti ↵Pavel Pisa2016-09-2216-0/+3519
| | | | | | | | | | | | | | | | | | | | HalCoGen generated files. The configuration is specific for TMS570LS3137 based HDK. Pins configuration can be easily changed in rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c file. The list tms570_selftest_par_list in the file rtems/c/src/lib/libbsp/arm/tms570/hwinit/bspstarthooks-hwinit.c specifies peripherals which health status is examined by parity self-test at BSP start-up. It can be easily modified for other TMS570 family members variants same as the selection of other tests in bspstarthooks-hwinit.c.
* arm/tms570: define base addresses of all TMS570LS3137 SPI interfaces.Pavel Pisa2016-09-221-1/+5
| | | | | | | | Generated header file ti_herc/reg_spi.h contains complete registers and fields set for Ti MibSPI peripheral. Care has to be taken that only TMS570_SPI1, TMS570_SPI3 and TMS570_SPI5 are of this complete multibuffer type. TMS570_SPI2 and TMS570_SPI4 have substantial part of registers removed but else they are compatible.
* bsps/arm: Export bsp_start_hook_0_done symbol from ARM start.S.Pavel Pisa2016-09-221-0/+1
| | | | | | | | The symbol can be used by bsp_start_hook_0 when complete RAM memory is initialization and overwritten during BSP self-test. The test overwrites even memory used to store return address / link register and regular resturn from bsp_start_hook_0 is not possible then.
* classic networking: adapt FXP driver to work with actual PCI and IRQ code.Pavel Pisa2016-09-212-106/+98
| | | | | | | | | | | Tested to work with QEMU provided Intel i82557b network controller emulation. qemu-system-x86_64 -enable-kvm -kernel $APP_BINARY \ -vga cirrus \ -append "--console=/dev/com1" \ -serial stdio \ -net nic,vlan=1,macaddr=be:be:be:10:00:01,model=i82557b \ -net tap,ifname=tap1,vlan=1,script=no,downscript=no
* classic networking: do not reference BSP_irq_enabled_at_i8259s which is no ↵Pavel Pisa2016-09-205-40/+5
| | | | | | | more available on i386. This change is required to build RTEMS with classic "--enable-networking" and link applications/tests which reference RTEMS_BSP_NETWORK_DRIVER_ATTACH.
* termios: Use IMFS nodes for new Termios devicesSebastian Huber2016-09-197-83/+21
| | | | | | | | This makes the new Termios devices independent of device major/minor numbers. It enables BSP independent Termios device drivers which may reside in the cpukit domain. These drivers require an IMFS and do not work with the device file system. However, the device file system should go away in the future.
* bsp/atsam: Add SPI bus driverAlexander Krutwig2016-09-166-0/+770
|
* bsp/atsam: Use normal memory for QSPI flash areaAlexander Krutwig2016-09-161-2/+2
| | | | This is a performance improvement for execute-in-place (XIP).
* arm/raspberrypi: define bsp_reset to restart board by watchdog.Pavel Pisa2016-09-083-1/+82
| | | | | Whether the board is restarted after application finish/exit is controlled by BSP_RESET_BOARD_AT_EXIT configure option.
* powerpc: Fix SMP context switchSebastian Huber2016-09-081-61/+62
| | | | | | We need the unmodified r4 for get_potential_new_heir. This partially reverts commit 8d785f72d9610fb80a65d7848404f0f7507e026c.
* testsuite: Add libdl/dl05 reloc test.Chris Johns2016-09-083-0/+3
|
* bsp/raspberrypi: Rename fileSebastian Huber2016-09-082-1/+1
|
* arm/raspberrypi: use GPU/system timer as clock source.Pavel Pisa2016-09-071-36/+62
| | | | | | It has advantage that it is designed as free-running counter with compare registers and can easily serve for for both timecounter and tick interrupt.
* arm/raspberrypi: correct and extend definitions for GPU timer.Pavel Pisa2016-09-072-7/+16
|
* arm/raspberrypi: basic BCM2836 SMP implementation.Pavel Pisa2016-09-078-4/+230
| | | | | | | | The BSP support is divided to startup/bspsmp_api.c file where functions required by SuperCore are defined and BCM2836 hardware initialization part in startup/bspsmp_init.c. Separation is done to prevent smpfatal08 test build failure.
* arm/raspberrypi: propagate number of configured CPUs into linker script.Pavel Pisa2016-09-072-0/+16
|
* arm/raspberrypi: rename linkcmds to linkcmds.in to allow their configure ↵Pavel Pisa2016-09-073-4/+3
| | | | processing.
* arm/raspberrypi: more definitions of BCM2836 core local peripherals.Pavel Pisa2016-09-071-2/+140
|
* arm/raspberrypi: include definitions of BCM2836 SMP mailboxes.Rohini Kulkarni2016-09-071-0/+26
|
* bsps/arm: reorganize CP15 code to allow clean and invalidate ARMv7 cache by ↵Pavel Pisa2016-09-071-48/+60
| | | | | | | level. New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level can be used to maintain single cache level (instruction or data).
* bsps/arm: remove lock in arm_cp15_set_translation_table_entries().Pavel Pisa2016-09-071-9/+1
| | | | | | | | | | | Protection by rtems_interrupt_disable() is incompatible with SMP build. Actual page table entries manipulation function does not need locking and disabling cache and can be run concurrently even on multiple CPUs as long as changes do not modify same region. If the function is called from more threads/CPUs to modify same region with different mapping options concurrently then there is problem at another level of virtual address space management and has to be solved by mutex or other locking at that level.
* bsps/arm: use defines for cache type register format field.Pavel Pisa2016-09-071-9/+30
| | | | | | The change documents meaning of codes and opens well defined way to use cache type format for cache examination/debugging outside of arm-cp15.h file.
* bsp/atsam: Add SDRAM IS42S16320F-7BL.Christian Mauderer2016-09-073-1/+56
|
* bsp/atsam: Move ram init values to structure.Christian Mauderer2016-09-074-0/+58
|
* bsp/xilinx-zynq: Avoid duplicate declarationSebastian Huber2016-09-061-1/+1
|
* arm/xilinx_zynq: Start the second core when an SMP build.Chris Johns2016-09-012-0/+22
|
* arm/xilinx_zynq: ensure that cache is cleaned and MMU disabled when ↵Pavel Pisa2016-09-011-0/+35
| | | | | | | | | initialization starts. The u-boot loader enables the MMU plus the data and instruction caches in some versions which results in RTEMS boot failure. Closes #2774.
* libdl: The dl04 is too big for some BSPs. Do not built it.Chris Johns2016-08-303-0/+3
|
* arm/raspberrypi: Mailbox : Extending functionalityMudit Jain2016-08-273-0/+130
| | | | | Adding functionality to get board serial, power state & clock rate
* bsp/atsam: Add missing break statementAlexander Krutwig2016-08-241-0/+1
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-25 03:04:02 +0000