summaryrefslogtreecommitdiffstats
path: root/bsps/sh/gensh4/start
diff options
context:
space:
mode:
Diffstat (limited to 'bsps/sh/gensh4/start')
-rw-r--r--bsps/sh/gensh4/start/bsp_specs9
-rw-r--r--bsps/sh/gensh4/start/cpu_asm.c105
-rw-r--r--bsps/sh/gensh4/start/ispsh7750.c317
-rw-r--r--bsps/sh/gensh4/start/linkcmds193
-rw-r--r--bsps/sh/gensh4/start/linkcmds.rom239
-rw-r--r--bsps/sh/gensh4/start/linkcmds.rom2ram243
6 files changed, 1106 insertions, 0 deletions
diff --git a/bsps/sh/gensh4/start/bsp_specs b/bsps/sh/gensh4/start/bsp_specs
new file mode 100644
index 0000000000..87638cc027
--- /dev/null
+++ b/bsps/sh/gensh4/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/sh/gensh4/start/cpu_asm.c b/bsps/sh/gensh4/start/cpu_asm.c
new file mode 100644
index 0000000000..52a033bb75
--- /dev/null
+++ b/bsps/sh/gensh4/start/cpu_asm.c
@@ -0,0 +1,105 @@
+/*
+ * This file contains the basic algorithms for all assembly code used
+ * in an specific CPU port of RTEMS. These algorithms must be implemented
+ * in assembly language
+ *
+ * NOTE: This port uses a C file with inline assembler instructions
+ *
+ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ * Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ * COPYRIGHT (c) 1998.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+/*
+ * This is supposed to be an assembly file. This means that system.h
+ * and cpu.h should not be included in a "real" cpu_asm file. An
+ * implementation in assembly should include "cpu_asm.h"
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/threaddispatch.h>
+#include <rtems/score/sh.h>
+#include <rtems/score/ispsh7750.h>
+#include <rtems/score/iosh7750.h>
+#include <rtems/score/sh4_regs.h>
+#include <rtems/score/sh_io.h>
+
+/* from cpu_isps.c */
+extern proc_ptr _Hardware_isr_Table[];
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+ unsigned long *_old_stack_ptr;
+#endif
+
+register unsigned long *stack_ptr __asm__ ("r15");
+
+/*
+ * This routine provides the RTEMS interrupt management.
+ */
+
+void __ISR_Handler( uint32_t vector)
+{
+ ISR_Level level;
+
+ _ISR_Local_disable( level );
+
+ _Thread_Dispatch_disable();
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+ if ( _ISR_Nest_level == 0 )
+ {
+ /* Install irq stack */
+ _old_stack_ptr = stack_ptr;
+ stack_ptr = _CPU_Interrupt_stack_high;
+ }
+
+#endif
+
+ _ISR_Nest_level++;
+
+ _ISR_Local_enable( level );
+
+ /* call isp */
+ if ( _ISR_Vector_table[ vector])
+ (*_ISR_Vector_table[ vector ])( vector );
+
+ _ISR_Local_disable( level );
+
+ _Thread_Dispatch_enable( _Per_CPU_Get() );
+
+ _ISR_Nest_level--;
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+ if ( _ISR_Nest_level == 0 )
+ /* restore old stack pointer */
+ stack_ptr = _old_stack_ptr;
+#endif
+
+ _ISR_Local_enable( level );
+
+ if ( _ISR_Nest_level )
+ return;
+
+ if ( !_Thread_Dispatch_is_enabled() ) {
+ return;
+ }
+
+ if ( _Thread_Dispatch_necessary ) {
+ _Thread_Dispatch();
+ }
+}
diff --git a/bsps/sh/gensh4/start/ispsh7750.c b/bsps/sh/gensh4/start/ispsh7750.c
new file mode 100644
index 0000000000..5a1282f583
--- /dev/null
+++ b/bsps/sh/gensh4/start/ispsh7750.c
@@ -0,0 +1,317 @@
+/*
+ * SH7750 interrupt support.
+ *
+ * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * Based on work:
+ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ * Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
+ *
+ *
+ * COPYRIGHT (c) 1998.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ *
+ * Modified to reflect isp entries for sh7045 processor:
+ * John M. Mills (jmills@tga.com)
+ * TGA Technologies, Inc.
+ * 100 Pinnacle Way, Suite 140
+ * Norcross, GA 30071 U.S.A.
+ * August, 1999
+ *
+ * This modified file may be copied and distributed in accordance
+ * the above-referenced license. It is provided for critique and
+ * developmental purposes without any warranty nor representation
+ * by the authors or by TGA Technologies.
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/isr.h>
+
+/*
+ * This is a exception vector table
+ *
+ * It has the same structure as the actual vector table (vectab)
+ */
+
+
+#include <rtems/score/ispsh7750.h>
+#include <rtems/score/sh4_regs.h>
+#include <rtems/score/sh7750_regs.h>
+
+/* VBR register contents saved on startup -- used to hook exception by debug
+ * agent */
+void *_VBR_Saved;
+
+#define __STRINGIFY1__(x) #x
+#define __STRINGIFY__(x) __STRINGIFY1__(x)
+
+#define STOP_TIMER \
+ " mov.l TSTR_k,r0 \n" \
+ " mov.b @r0,r1 \n" \
+ " and #" __STRINGIFY__(~SH7750_TSTR_STR0) ",r1\n" \
+ " mov.b r1,@r0 \n"
+
+#define START_TIMER \
+ " mov.l TSTR_k,r0 \n" \
+ " mov.b @r0,r1 \n" \
+ " or #" __STRINGIFY__(SH7750_TSTR_STR0) ",r1\n" \
+ " mov.b r1,@r0 \n"
+
+__asm__ (" .text\n"
+ " .balign 256\n"
+ " .global __vbr_base\n"
+ "__vbr_base:\n"
+ " .org __vbr_base + 0x100\n"
+ "vbr_100:\n"
+ " mov.l r0,@-r15\n"
+ " mov.l r1,@-r15\n"
+ " mov.l __VBR_Saved100_k, r0\n"
+ " mov.l offset100_k,r1\n"
+ " mov.l @r0,r0\n"
+ " add r1,r0\n"
+ " mov.l @r15+,r1\n"
+ " jmp @r0\n"
+ " mov.l @r15+,r0\n"
+ " .align 2\n"
+ "__VBR_Saved100_k:\n"
+ " .long __VBR_Saved\n"
+ "offset100_k:\n"
+ " .long 0x100\n"
+
+ " .org __vbr_base + 0x400\n"
+ "vbr_400:\n"
+ " mov.l r0,@-r15\n"
+ " mov.l r1,@-r15\n"
+ " mov.l __VBR_Saved400_k, r0\n"
+ " mov.l offset400_k,r1\n"
+ " mov.l @r0,r0\n"
+ " add r1,r0\n"
+ " mov.l @r15+,r1\n"
+ " jmp @r0\n"
+ " mov.l @r15+,r0\n"
+ " .align 2\n"
+ "__VBR_Saved400_k:\n"
+ " .long __VBR_Saved\n"
+ "offset400_k:\n"
+ " .long 0x400\n"
+
+ " .org __vbr_base + 0x600\n"
+ "vbr_600:\n"
+ " mov.l r0,@-r15 \n"
+ " mov.l r1,@-r15 \n"
+ " stc sr,r0 \n"
+ " mov.l __vbr_600_sr_and_k,r1\n"
+ " and r1,r0 \n"
+ " mov.l __vbr_600_sr_or_k,r1\n"
+ " or r1,r0 \n"
+ " ldc r0,sr \n"
+ " ldc.l @r15+,r1_bank\n"
+ " ldc.l @r15+,r0_bank\n"
+ " mov.l r0,@-r15 \n"
+ " mov.l r1,@-r15 \n"
+ " mov.l r2,@-r15 \n"
+ " mov.l r3,@-r15 \n"
+ " mov.l r4,@-r15 \n"
+ " mov.l r5,@-r15 \n"
+ " mov.l r6,@-r15 \n"
+ " mov.l r7,@-r15 \n"
+#if 0
+ " mov.l r8,@-r15 \n"
+ " mov.l r9,@-r15 \n"
+ " mov.l r10,@-r15 \n"
+ " mov.l r11,@-r15 \n"
+ " mov.l r12,@-r15 \n"
+ " mov.l r13,@-r15 \n"
+#endif
+ " mov.l r14,@-r15 \n"
+ " sts.l fpscr,@-r15\n"
+ " sts.l fpul,@-r15 \n"
+ " mov.l __ISR_temp_fpscr_k,r0 \n"
+ " lds r0,fpscr \n"
+ " fmov fr0,@-r15 \n"
+ " fmov fr1,@-r15 \n"
+ " fmov fr2,@-r15 \n"
+ " fmov fr3,@-r15 \n"
+ " fmov fr4,@-r15 \n"
+ " fmov fr5,@-r15 \n"
+ " fmov fr6,@-r15 \n"
+ " fmov fr7,@-r15 \n"
+ " fmov fr8,@-r15 \n"
+ " fmov fr9,@-r15 \n"
+ " fmov fr10,@-r15 \n"
+ " fmov fr11,@-r15 \n"
+ " fmov fr12,@-r15 \n"
+ " fmov fr13,@-r15 \n"
+ " fmov fr14,@-r15 \n"
+ " fmov fr15,@-r15 \n"
+
+ " sts.l pr,@-r15 \n"
+ " sts.l mach,@-r15 \n"
+ " sts.l macl,@-r15 \n"
+ " stc.l spc,@-r15 \n"
+ " stc.l ssr,@-r15 \n"
+ " mov r15,r14 \n"
+#if 0
+ " stc ssr,r0 \n"
+ " ldc r0,sr \n"
+#endif
+ " mov.l __ISR_Handler_k, r1\n"
+ " mov.l _INTEVT_k,r4\n"
+ " mov.l @r4,r4 \n"
+ " shlr2 r4 \n"
+ " shlr r4 \n"
+
+ " mov.l _ISR_Table_k,r0\n"
+ " mov.l @r0,r0 \n"
+ " add r4,r0 \n"
+ " mov.l @r0,r0 \n"
+ " cmp/eq #0,r0 \n"
+ " bt _ipl_hook \n"
+
+
+ " jsr @r1 \n"
+ " shlr2 r4 \n"
+ " mov r14,r15 \n"
+ " ldc.l @r15+,ssr \n"
+ " ldc.l @r15+,spc \n"
+ " lds.l @r15+,macl \n"
+ " lds.l @r15+,mach \n"
+ " lds.l @r15+,pr \n"
+ " mov.l __ISR_temp_fpscr_k,r0 \n"
+ " lds r0,fpscr \n"
+
+ " fmov @r15+,fr15 \n"
+ " fmov @r15+,fr14 \n"
+ " fmov @r15+,fr13 \n"
+ " fmov @r15+,fr12 \n"
+ " fmov @r15+,fr11 \n"
+ " fmov @r15+,fr10 \n"
+ " fmov @r15+,fr9 \n"
+ " fmov @r15+,fr8 \n"
+ " fmov @r15+,fr7 \n"
+ " fmov @r15+,fr6 \n"
+ " fmov @r15+,fr5 \n"
+ " fmov @r15+,fr4 \n"
+ " fmov @r15+,fr3 \n"
+ " fmov @r15+,fr2 \n"
+ " fmov @r15+,fr1 \n"
+ " fmov @r15+,fr0 \n"
+ " lds.l @r15+,fpul \n"
+ " lds.l @r15+,fpscr\n"
+ " mov.l @r15+,r14 \n"
+#if 0
+ " mov.l @r15+,r13 \n"
+ " mov.l @r15+,r12 \n"
+ " mov.l @r15+,r11 \n"
+ " mov.l @r15+,r10 \n"
+ " mov.l @r15+,r9 \n"
+ " mov.l @r15+,r8 \n"
+#endif
+
+ " mov.l @r15+,r7 \n"
+ " mov.l @r15+,r6 \n"
+ " mov.l @r15+,r5 \n"
+ " mov.l @r15+,r4 \n"
+ " mov.l @r15+,r3 \n"
+ " mov.l @r15+,r2 \n"
+ " mov.l @r15+,r1 \n"
+ " mov.l @r15+,r0 \n"
+ " rte \n"
+ " nop \n"
+ " .align 2 \n"
+ "__vbr_600_sr_and_k: \n"
+ " .long " __STRINGIFY__(~(SH4_SR_RB | SH4_SR_BL)) "\n"
+ "__vbr_600_sr_or_k: \n"
+ " .long " __STRINGIFY__(SH4_SR_IMASK) "\n"
+ "__ISR_Handler_k: \n"
+ " .long ___ISR_Handler\n"
+ "_INTEVT_k: \n"
+ " .long " __STRINGIFY__(SH7750_INTEVT) "\n"
+ "_ISR_Table_k: \n"
+ " .long __ISR_Vector_table\n"
+
+ "_ipl_hook: \n"
+ " mov r14,r15 \n"
+ " ldc.l @r15+,ssr \n"
+ " ldc.l @r15+,spc \n"
+ " lds.l @r15+,macl \n"
+ " lds.l @r15+,mach \n"
+ " lds.l @r15+,pr \n"
+ " mov.l __ISR_temp_fpscr_k,r0 \n"
+ " lds r0,fpscr \n"
+ " fmov @r15+,fr15 \n"
+ " fmov @r15+,fr14 \n"
+ " fmov @r15+,fr13 \n"
+ " fmov @r15+,fr12 \n"
+ " fmov @r15+,fr11 \n"
+ " fmov @r15+,fr10 \n"
+ " fmov @r15+,fr9 \n"
+ " fmov @r15+,fr8 \n"
+ " fmov @r15+,fr7 \n"
+ " fmov @r15+,fr6 \n"
+ " fmov @r15+,fr5 \n"
+ " fmov @r15+,fr4 \n"
+ " fmov @r15+,fr3 \n"
+ " fmov @r15+,fr2 \n"
+ " fmov @r15+,fr1 \n"
+ " fmov @r15+,fr0 \n"
+ " lds.l @r15+,fpul \n"
+ " lds.l @r15+,fpscr\n"
+ " mov.l @r15+,r14 \n"
+
+ " mov.l @r15+,r13 \n"
+ " mov.l @r15+,r12 \n"
+ " mov.l @r15+,r11 \n"
+ " mov.l @r15+,r10 \n"
+ " mov.l @r15+,r9 \n"
+ " mov.l @r15+,r8 \n"
+
+
+ " mov.l @r15+,r7 \n"
+ " mov.l @r15+,r6 \n"
+ " mov.l @r15+,r5 \n"
+ " mov.l @r15+,r4 \n"
+ " mov.l @r15+,r3 \n"
+ " mov.l @r15+,r2 \n"
+ " mov.l __VBR_Saved600_k, r0\n"
+ " mov.l offset600_k,r1\n"
+ " mov.l @r0,r0\n"
+ " add r1,r0\n"
+ " mov.l @r15+,r1\n"
+ " jmp @r0\n"
+ " mov.l @r15+,r0\n"
+ " .align 2\n"
+ "__ISR_temp_fpscr_k: \n"
+ " .long " __STRINGIFY__(SH4_FPSCR_PR) " \n"
+ "__VBR_Saved600_k:\n"
+ " .long __VBR_Saved\n"
+ "offset600_k:\n"
+ " .long 0x600\n"
+
+ );
+
+
+/************************************************
+ * Dummy interrupt service procedure for
+ * interrupts being not allowed --> Trap 2
+ ************************************************/
+__asm__ (" .section .text\n\
+.global __dummy_isp\n\
+__dummy_isp:\n\
+ mov.l r14,@-r15\n\
+ mov r15, r14\n\
+ trapa #2\n\
+ mov.l @r15+,r14\n\
+ rte\n\
+ nop");
diff --git a/bsps/sh/gensh4/start/linkcmds b/bsps/sh/gensh4/start/linkcmds
new file mode 100644
index 0000000000..de6bb05693
--- /dev/null
+++ b/bsps/sh/gensh4/start/linkcmds
@@ -0,0 +1,193 @@
+/*
+ * This file contains GNU linker directives for an general SH4
+ * board.
+ *
+ * Variations in memory size and allocation can be made by
+ * overriding some values with linker command-line arguments.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x80000000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 4M;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+
+/*
+ * Area assignments:
+ * Area 0: Flash memory, SRAM interface
+ * Area 1: GDC
+ * Area 2: SDRAM
+ * Area 3-6: unused
+ */
+MEMORY
+{
+ ram : o = 0x88100000, l = 7M
+ rom : o = 0x80000000, l = 4M
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ _start = .;
+ *(.text*)
+
+ /*
+ * Special FreeBSD sysctl sections.
+ */
+ . = ALIGN (16);
+ ___start_set_sysctl_set = .;
+ *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */
+ ___stop_set_sysctl_set = ABSOLUTE(.);
+ *(set_doma*); /* set_domain_* but name is truncated by SH-coff */
+ *(set_pseu*); /* set_pseudo_* but name is truncated by SH-coff */
+
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.gnu.linkonce.t*)
+ } > ram
+ .rela.dyn :
+ {
+ *(.rela.init)
+ *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+ *(.rela.fini)
+ *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+ *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+ *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+ *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+ *(.rela.ctors)
+ *(.rela.dtors)
+ *(.rela.got)
+ *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+ *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+ *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+ *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+ *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+ } >ram
+ _etext = .;
+ PROVIDE (etext = .);
+ .init . : { KEEP(*(.init)) } > ram =0
+ .fini . : { KEEP(*(.fini)) } > ram =0
+ .ctors . : { KEEP(*(.ctors)) } > ram =0
+ .dtors . : { KEEP(*(.dtors)) } > ram =0
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ KEEP (*(SORT(.rtemsroset.*)))
+ *(.gnu.linkonce.r*)
+ } > ram
+ .tdata : {
+ __TLS_Data_begin = .;
+ *(.tdata .tdata.* .gnu.linkonce.td.*)
+ __TLS_Data_end = .;
+ } > ram
+ .tbss : {
+ __TLS_BSS_begin = .;
+ *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+ __TLS_BSS_end = .;
+ } > ram
+ __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+ __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+ __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+ __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+ __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+ __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+
+ /* Adjust the address for the data segment. We want to adjust up to
+ the same address within the page on the next page up. */
+ . = ALIGN(128) + (. & (128 - 1));
+ .data :
+ {
+ copy_start = .;
+ *(.data*)
+ KEEP (*(SORT(.rtemsrwset.*)))
+ *(.gcc_exc*)
+ ___EH_FRAME_BEGIN__ = .;
+ *(.eh_fram*)
+ ___EH_FRAME_END__ = .;
+ LONG(0);
+ *(.gcc_except_table*)
+ *(.gnu.linkonce.d*)
+ SORT(CONSTRUCTORS)
+ copy_end = .;
+ } > ram
+ .eh_frame : { *(.eh_frame) } > ram
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ .bss :
+ {
+ __bss_start = .;
+ *(.dynbss)
+ *(.bss .bss* .gnu.linkonce.b*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections. */
+ . = ALIGN(32 / 8);
+ __bss_end = .;
+ } > ram
+
+ .stack . : {
+ . = . + 4096;
+ }
+
+ . = ALIGN(16);
+ _WorkAreaBase = . ;
+
+ . = ALIGN(16);
+ _CPU_Interrupt_stack_low = . ;
+ _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .stack : { _stack = .; *(.stack) }
+ /* These must appear regardless of . */
+}
diff --git a/bsps/sh/gensh4/start/linkcmds.rom b/bsps/sh/gensh4/start/linkcmds.rom
new file mode 100644
index 0000000000..13c6096af1
--- /dev/null
+++ b/bsps/sh/gensh4/start/linkcmds.rom
@@ -0,0 +1,239 @@
+/*
+ * This file contains GNU linker directives for an general SH4
+ * board.
+ *
+ * Variations in memory size and allocation can be made by
+ * overriding some values with linker command-line arguments.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+
+OUTPUT_FORMAT("elf32-shl", "elf32-shl",
+ "elf32-shl")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x88000000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 8M;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : (2 * 1024 * 1024);
+
+/*
+ * Area assignments:
+ * Area 0: Flash memory, SRAM interface
+ * Area 1: GDC
+ * Area 2: SDRAM
+ * Area 3-6: unused
+ */
+MEMORY
+{
+/*
+ * Real values
+ */
+ ram : o = 0x88000000, l = 8M
+ rom : o = 0x80000000, l = 4M
+/*
+ * Fake values to test from gdb
+ */
+/*
+ ram : o = 0x88100000, l = 4M
+ rom : o = 0x88500000, l = 3M
+*/
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .init :
+ {
+ KEEP (*(.init))
+ } =0
+ .text :
+ {
+ *(.text*)
+
+ /*
+ * Special FreeBSD sysctl sections.
+ */
+ . = ALIGN (16);
+ ___start_set_sysctl_set = .;
+ *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */
+ ___stop_set_sysctl_set = ABSOLUTE(.);
+ *(set_doma*); /* set_domain_* but name is truncated by SH-coff */
+ *(set_pseudo_*);
+
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.gnu.linkonce.t*)
+ } > rom
+ _etext = .;
+ PROVIDE (etext = .);
+ .rela.dyn :
+ {
+ *(.rela.init)
+ *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+ *(.rela.fini)
+ *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+ *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+ *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+ *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+ *(.rela.ctors)
+ *(.rela.dtors)
+ *(.rela.got)
+ *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+ *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+ *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+ *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+ *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+ } >ram
+ .fini :
+ {
+ KEEP (*(.fini))
+ } =0
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ KEEP (*(SORT(.rtemsroset.*)))
+ *(.gnu.linkonce.r*)
+ . = ALIGN(32);
+ } > rom
+ .tdata : {
+ __TLS_Data_begin = .;
+ *(.tdata .tdata.* .gnu.linkonce.td.*)
+ __TLS_Data_end = .;
+ } > rom
+ .tbss : {
+ __TLS_BSS_begin = .;
+ *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+ __TLS_BSS_end = .;
+ } > rom
+ __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+ __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+ __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+ __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+ __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+ __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+ .ctors :
+ {
+ ___ctors = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ ___ctors_end = .;
+ } > rom
+ .dtors :
+ {
+ ___dtors = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ ___dtors_end = .;
+ copy_start_in_rom = .;
+ } > rom
+
+ /* Adjust the address for the data segment. We want to adjust up to
+ the same address within the page on the next page up. */
+ . = ALIGN(128) + (. & (128 - 1));
+ .data : AT(LOADADDR(.dtors) + SIZEOF(.dtors))
+ {
+ copy_start = .;
+ *(.data)
+ *(.data.*)
+ KEEP (*(SORT(.rtemsrwset.*)))
+ *(.gnu.linkonce.d*)
+ SORT(CONSTRUCTORS)
+ copy_end = .;
+ } > ram
+ .eh_frame : { *(.eh_frame) } > ram
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ .bss :
+ {
+ __bss_start = .;
+ *(.dynbss)
+ *(.bss .bss* .gnu.linkonce.b*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections. */
+ . = ALIGN(32 / 8);
+ __bss_end = .;
+ } > ram
+
+ . = ALIGN(16);
+ _WorkAreaBase = . ;
+
+ . = ALIGN(16);
+ .stack . : {
+ stack_start = .;
+ . = . + 4096;
+ stack_end = .;
+ }
+
+ . = ALIGN(16);
+ _CPU_Interrupt_stack_low = . ;
+ _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .stack : { _stack = .; *(.stack) }
+ /* These must appear regardless of . */
+}
diff --git a/bsps/sh/gensh4/start/linkcmds.rom2ram b/bsps/sh/gensh4/start/linkcmds.rom2ram
new file mode 100644
index 0000000000..cc14d4e98d
--- /dev/null
+++ b/bsps/sh/gensh4/start/linkcmds.rom2ram
@@ -0,0 +1,243 @@
+/*
+ * This file contains GNU linker directives for an general SH4
+ * board.
+ *
+ * Variations in memory size and allocation can be made by
+ * overriding some values with linker command-line arguments.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+
+OUTPUT_FORMAT("elf32-shl", "elf32-shl",
+ "elf32-shl")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x88000000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 8M;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : (2 * 1024 * 1024);
+
+/*
+ * Area assignments:
+ * Area 0: Flash memory, SRAM interface
+ * Area 1: GDC
+ * Area 2: SDRAM
+ * Area 3-6: unused
+ */
+MEMORY
+{
+/*
+ * Real values
+ */
+ ram : o = 0x88000000, l = 8M
+ rom : o = 0x80000000, l = 4M
+/*
+ * Fake values to test from gdb
+ */
+/*
+ ram : o = 0x88100000, l = 4M
+ rom : o = 0x88500000, l = 3M
+*/
+}
+
+SECTIONS
+{
+ rom : {
+ copy_start_in_rom = .;
+ } >rom
+
+ /* Read-only sections, merged into text segment: */
+ .init :
+ {
+ KEEP (*(.init))
+ } =0
+ .text : AT(copy_start_in_rom)
+ {
+ copy_start = .;
+ *(.text*)
+
+ /*
+ * Special FreeBSD sysctl sections.
+ */
+ . = ALIGN (16);
+ ___start_set_sysctl_set = .;
+ *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */
+ ___stop_set_sysctl_set = ABSOLUTE(.);
+ *(set_doma*); /* set_domain_* but name is truncated by SH-coff */
+ *(set_pseudo_*);
+
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.gnu.linkonce.t*)
+ } > ram
+ _etext = .;
+ PROVIDE (etext = .);
+ .fini :
+ {
+ KEEP (*(.fini))
+ } =0
+ .rodata : AT(LOADADDR(.text) + SIZEOF(.text))
+ {
+ *(.rodata)
+ *(.rodata.*)
+ KEEP (*(SORT(.rtemsroset.*)))
+ *(.gnu.linkonce.r*)
+ . = ALIGN(32);
+ } > ram
+ .tdata : {
+ __TLS_Data_begin = .;
+ *(.tdata .tdata.* .gnu.linkonce.td.*)
+ __TLS_Data_end = .;
+ } > ram
+ .tbss : {
+ __TLS_BSS_begin = .;
+ *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+ __TLS_BSS_end = .;
+ } > ram
+ __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+ __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+ __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+ __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+ __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+ __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+ .ctors : AT(LOADADDR(.rodata) + SIZEOF(.rodata))
+ {
+ ___ctors = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ ___ctors_end = .;
+ } > ram
+ .dtors : AT(LOADADDR(.ctors) + SIZEOF(.ctors))
+ {
+ ___dtors = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ ___dtors_end = .;
+ } > ram
+
+ /* Adjust the address for the data segment. We want to adjust up to
+ the same address within the page on the next page up. */
+ . = ALIGN(128) + (. & (128 - 1));
+ .data : AT(LOADADDR(.dtors) + SIZEOF(.dtors))
+ {
+ *(.data)
+ *(.data.*)
+ KEEP (*(SORT(.rtemsrwset.*)))
+ *(.gnu.linkonce.d*)
+ SORT(CONSTRUCTORS)
+ copy_end = .;
+ } > ram
+ .eh_frame : { *(.eh_frame) } > ram
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ .bss :
+ {
+ __bss_start = .;
+ *(.dynbss)
+ *(.bss .bss* .gnu.linkonce.b*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections. */
+ . = ALIGN(32 / 8);
+ __bss_end = .;
+ } > ram
+
+ .rela.dyn :
+ {
+ *(.rela.init)
+ *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+ *(.rela.fini)
+ *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+ *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+ *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+ *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+ *(.rela.ctors)
+ *(.rela.dtors)
+ *(.rela.got)
+ *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+ *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+ *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+ *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+ *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+ } >ram
+ . = ALIGN(16);
+
+ _WorkAreaBase = . ;
+
+ . = ALIGN(16);
+ .stack . : {
+ stack_start = .;
+ . = . + 4096;
+ stack_end = .;
+ }
+
+ . = ALIGN(16);
+ _CPU_Interrupt_stack_low = . ;
+ _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .stack : { _stack = .; *(.stack) }
+ /* These must appear regardless of . */
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 21:03:54 +0000