diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-01-13 11:38:18 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-01-13 11:38:18 +0100 |
| commit | f2e6c3e84afe25f6c94b1073f60dbbcd99a3472b (patch) | |
| tree | 1bd5fba5d71f7224b0acecd0c4c8c4434b129434 | |
| parent | powerpc: AltiVec and FPU context support (diff) | |
| download | rtems-f2e6c3e84afe25f6c94b1073f60dbbcd99a3472b.tar.bz2 | |
bsp/qoriq: Add T2080RDB and T4240RDB variants
24 files changed, 714 insertions, 318 deletions
diff --git a/c/src/lib/libbsp/powerpc/qoriq/Makefile.am b/c/src/lib/libbsp/powerpc/qoriq/Makefile.am index a87f296706..dea5964042 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/Makefile.am +++ b/c/src/lib/libbsp/powerpc/qoriq/Makefile.am @@ -25,6 +25,7 @@ include_bsp_HEADERS = include/irq.h \ ../../shared/include/u-boot.h \ ../../shared/include/utility.h \ ../shared/include/u-boot-board-info.h \ + ../shared/include/u-boot-generic-board-info.h \ ../shared/include/start.h \ ../shared/include/tictac.h \ ../shared/include/linker-symbols.h \ @@ -46,7 +47,9 @@ dist_project_lib_DATA += startup/linkcmds \ ../shared/startup/linkcmds.base \ startup/linkcmds.qoriq_core_0 \ startup/linkcmds.qoriq_core_1 \ - startup/linkcmds.qoriq_p1020rdb + startup/linkcmds.qoriq_p1020rdb \ + startup/linkcmds.qoriq_t2080rdb \ + startup/linkcmds.qoriq_t4240rdb noinst_LIBRARIES += libbsp.a libbsp_a_SOURCES = diff --git a/c/src/lib/libbsp/powerpc/qoriq/configure.ac b/c/src/lib/libbsp/powerpc/qoriq/configure.ac index 18a26f63a4..f1ff103d7c 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/configure.ac +++ b/c/src/lib/libbsp/powerpc/qoriq/configure.ac @@ -28,6 +28,24 @@ RTEMS_BSPOPTS_SET([PPC_EXC_CONFIG_BOOKE_ONLY],[*],[1]) RTEMS_BSPOPTS_HELP([PPC_EXC_CONFIG_BOOKE_ONLY], [only support Book E exception types]) +RTEMS_BSPOPTS_SET([PPC_CACHE_ALIGNMENT],[qoriq_t*],[64]) +RTEMS_BSPOPTS_SET([PPC_CACHE_ALIGNMENT],[*],[]) +RTEMS_BSPOPTS_HELP([PPC_CACHE_ALIGNMENT],[the cache alignment]) + +RTEMS_BSPOPTS_SET([PPC_CACHE_DATA_L1_SIZE],[*],[(32 * 1024)]) +RTEMS_BSPOPTS_HELP([PPC_CACHE_DATA_L1_SIZE],[the L1 data cache size]) + +RTEMS_BSPOPTS_SET([PPC_CACHE_DATA_L2_SIZE],[qoriq_t*],[(2048 * 1024)]) +RTEMS_BSPOPTS_SET([PPC_CACHE_DATA_L2_SIZE],[*],[(256 * 1024)]) +RTEMS_BSPOPTS_HELP([PPC_CACHE_DATA_L2_SIZE],[the L2 data cache size]) + +RTEMS_BSPOPTS_SET([PPC_CACHE_INSTRUCTION_L1_SIZE],[*],[(32 * 1024)]) +RTEMS_BSPOPTS_HELP([PPC_CACHE_INSTRUCTION_L1_SIZE],[the L1 instruction cache size]) + +RTEMS_BSPOPTS_SET([PPC_CACHE_INSTRUCTION_L2_SIZE],[qoriq_t*],[(2048 * 1024)]) +RTEMS_BSPOPTS_SET([PPC_CACHE_INSTRUCTION_L2_SIZE],[*],[(256 * 1024)]) +RTEMS_BSPOPTS_HELP([PPC_CACHE_INSTRUCTION_L2_SIZE],[the L2 instruction cache size]) + RTEMS_BSPOPTS_SET([BSP_CONSOLE_BAUD],[*],[115200]) RTEMS_BSPOPTS_HELP([BSP_CONSOLE_BAUD],[default baud for console and other serial devices]) @@ -37,6 +55,40 @@ RTEMS_BSPOPTS_HELP([BSP_USE_UART_INTERRUPTS],[enable usage of interrupts for the RTEMS_BSPOPTS_SET([HAS_UBOOT],[*],[1]) RTEMS_BSPOPTS_HELP([HAS_UBOOT],[enables U-Boot support]) +RTEMS_BSPOPTS_SET([U_BOOT_64_BIT_PHYS_SIZE],[qoriq_t*],[1]) +RTEMS_BSPOPTS_SET([U_BOOT_64_BIT_PHYS_SIZE],[*],[]) +RTEMS_BSPOPTS_HELP([U_BOOT_64_BIT_PHYS_SIZE],[if defined, then use uint64_t for phys_size_t]) + +RTEMS_BSPOPTS_SET([U_BOOT_GENERIC_BOARD_INFO],[qoriq_t*],[1]) +RTEMS_BSPOPTS_SET([U_BOOT_GENERIC_BOARD_INFO],[*],[]) +RTEMS_BSPOPTS_HELP([U_BOOT_GENERIC_BOARD_INFO],[if defined, then use the generic bd_t structure]) + +RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_BEGIN],[qoriq_p2020*],[0x3fff0000]) +RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_BEGIN],[qoriq_t2080*],[0x7fef4000]) +RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_BEGIN],[qoriq_t4240*],[0x7ff33000]) +RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_BEGIN],[*],[0x1fff0000]) +RTEMS_BSPOPTS_HELP([U_BOOT_BOOT_PAGE_BEGIN],[the begin address of the boot page set up by U-Boot]) + +RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_LAST],[qoriq_p2020*],[0x3fffffff]) +RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_LAST],[qoriq_t2080*],[0x7fef4fff]) +RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_LAST],[qoriq_t4240*],[0x7ff33fff]) +RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_LAST],[*],[0x1fffffff]) +RTEMS_BSPOPTS_HELP([U_BOOT_BOOT_PAGE_LAST],[the last address of the boot page set up by U-Boot]) + +RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_SPIN_OFFSET],[qoriq_p2020*],[0xf240]) +RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_SPIN_OFFSET],[qoriq_t*],[0x0200]) +RTEMS_BSPOPTS_SET([U_BOOT_BOOT_PAGE_SPIN_OFFSET],[*],[0xf2a0]) +RTEMS_BSPOPTS_HELP([U_BOOT_BOOT_PAGE_SPIN_OFFSET],[the offset to the spin table in the boot page set up by U-Boot]) + +RTEMS_BSPOPTS_SET([QORIQ_CPU_COUNT],[qoriq_t2080*],[8]) +RTEMS_BSPOPTS_SET([QORIQ_CPU_COUNT],[qoriq_t4240*],[24]) +RTEMS_BSPOPTS_SET([QORIQ_CPU_COUNT],[*],[2]) +RTEMS_BSPOPTS_HELP([QORIQ_CPU_COUNT],[virtual processor count]) + +RTEMS_BSPOPTS_SET([QORIQ_THREAD_COUNT],[qoriq_t*],[2]) +RTEMS_BSPOPTS_SET([QORIQ_THREAD_COUNT],[*],[1]) +RTEMS_BSPOPTS_HELP([QORIQ_THREAD_COUNT],[the number of threads per processor]) + RTEMS_BSPOPTS_SET([QORIQ_ETSEC_1_PHY_ADDR],[*],[-1]) RTEMS_BSPOPTS_HELP([QORIQ_ETSEC_1_PHY_ADDR],[PHY address for eTSEC interface 1]) @@ -46,14 +98,12 @@ RTEMS_BSPOPTS_HELP([QORIQ_ETSEC_2_PHY_ADDR],[PHY address for eTSEC interface 2]) RTEMS_BSPOPTS_SET([QORIQ_ETSEC_3_PHY_ADDR],[*],[1]) RTEMS_BSPOPTS_HELP([QORIQ_ETSEC_3_PHY_ADDR],[PHY address for eTSEC interface 3]) -RTEMS_BSPOPTS_SET([QORIQ_UART_0_ENABLE],[qoriq_core_0],[1]) -RTEMS_BSPOPTS_SET([QORIQ_UART_0_ENABLE],[qoriq_p1020rdb],[1]) -RTEMS_BSPOPTS_SET([QORIQ_UART_0_ENABLE],[*],[0]) +RTEMS_BSPOPTS_SET([QORIQ_UART_0_ENABLE],[qoriq_core_1],[0]) +RTEMS_BSPOPTS_SET([QORIQ_UART_0_ENABLE],[*],[1]) RTEMS_BSPOPTS_HELP([QORIQ_UART_0_ENABLE],[use 1 to enable UART 0, otherwise use 0]) -RTEMS_BSPOPTS_SET([QORIQ_UART_1_ENABLE],[qoriq_core_0],[1]) -RTEMS_BSPOPTS_SET([QORIQ_UART_1_ENABLE],[qoriq_p1020rdb],[1]) -RTEMS_BSPOPTS_SET([QORIQ_UART_1_ENABLE],[*],[0]) +RTEMS_BSPOPTS_SET([QORIQ_UART_1_ENABLE],[qoriq_core_1],[0]) +RTEMS_BSPOPTS_SET([QORIQ_UART_1_ENABLE],[*],[1]) RTEMS_BSPOPTS_HELP([QORIQ_UART_1_ENABLE],[use 1 to enable UART 1, otherwise use 0]) RTEMS_BSPOPTS_SET([QORIQ_UART_BRIDGE_MASTER_CORE],[*],[0]) @@ -84,12 +134,19 @@ RTEMS_BSPOPTS_HELP([QORIQ_INTERCOM_AREA_BEGIN],[inter-processor communication ar RTEMS_BSPOPTS_SET([QORIQ_INTERCOM_AREA_SIZE],[*],[0x1000000]) RTEMS_BSPOPTS_HELP([QORIQ_INTERCOM_AREA_SIZE],[inter-processor communication area size]) +RTEMS_BSPOPTS_SET([QORIQ_TLB1_ENTRY_COUNT],[qoriq_t*],[64]) +RTEMS_BSPOPTS_SET([QORIQ_TLB1_ENTRY_COUNT],[*],[16]) +RTEMS_BSPOPTS_HELP([QORIQ_TLB1_ENTRY_COUNT],[TLB1 entry count]) + +RTEMS_BSPOPTS_SET([QORIQ_INITIAL_MSR],[qoriq_t*],[0x02002200]) RTEMS_BSPOPTS_SET([QORIQ_INITIAL_MSR],[*],[0x02000200]) RTEMS_BSPOPTS_HELP([QORIQ_INITIAL_MSR],[initial MSR value]) +RTEMS_BSPOPTS_SET([QORIQ_INITIAL_SPEFSCR],[qoriq_t*],[]) RTEMS_BSPOPTS_SET([QORIQ_INITIAL_SPEFSCR],[*],[0x00000000]) RTEMS_BSPOPTS_HELP([QORIQ_INITIAL_SPEFSCR],[initial SPEFSCR value]) +RTEMS_BSPOPTS_SET([QORIQ_MMU_DEVICE_MAS7],[qoriq_t*],[0xf]) RTEMS_BSPOPTS_SET([QORIQ_MMU_DEVICE_MAS7],[*],[0x0]) RTEMS_BSPOPTS_HELP([QORIQ_MMU_DEVICE_MAS7],[MAS7 value for device TLB1 entries]) @@ -97,6 +154,15 @@ RTEMS_BSPOPTS_SET([QORIQ_CLOCK_TIMER],[qoriq_core_1],[4]) RTEMS_BSPOPTS_SET([QORIQ_CLOCK_TIMER],[*],[0]) RTEMS_BSPOPTS_HELP([QORIQ_CLOCK_TIMER],[global timer used for system clock, 0..3 maps to A0..A3, and 4..7 maps to B0..B3]) +RTEMS_BSPOPTS_SET([QORIQ_CHIP_VARIANT],[qoriq_t2080*],[QORIQ_CHIP_T2080]) +RTEMS_BSPOPTS_SET([QORIQ_CHIP_VARIANT],[qoriq_t4240*],[QORIQ_CHIP_T4240]) +RTEMS_BSPOPTS_SET([QORIQ_CHIP_VARIANT],[*],[QORIQ_CHIP_P1020]) +RTEMS_BSPOPTS_HELP([QORIQ_CHIP_VARIANT],[chip variant, use one of the defines QORIQ_CHIP_P1020, QORIQ_CHIP_T2080 or QORIQ_CHIP_T4240]) + +RTEMS_BSPOPTS_SET([QORIQ_BUS_CLOCK_DIVIDER],[qoriq_t*],[2]) +RTEMS_BSPOPTS_SET([QORIQ_BUS_CLOCK_DIVIDER],[*],[1]) +RTEMS_BSPOPTS_HELP([QORIQ_BUS_CLOCK_DIVIDER],[divider of the platform clock to get the clock most on-chip peripherals]) + RTEMS_CHECK_NETWORKING AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") diff --git a/c/src/lib/libbsp/powerpc/qoriq/console/console-config.c b/c/src/lib/libbsp/powerpc/qoriq/console/console-config.c index 352b118c2a..84868919ab 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/console/console-config.c +++ b/c/src/lib/libbsp/powerpc/qoriq/console/console-config.c @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -66,7 +66,7 @@ static ns16550_context qoriq_uart_context_0 = { .get_reg = get_register, .set_reg = set_register, .port = (uintptr_t) &qoriq.uart_0, - .irq = QORIQ_IRQ_DUART, + .irq = QORIQ_IRQ_DUART_1, .initial_baud = BSP_CONSOLE_BAUD }; #endif @@ -77,7 +77,7 @@ static ns16550_context qoriq_uart_context_1 = { .get_reg = get_register, .set_reg = set_register, .port = (uintptr_t) &qoriq.uart_1, - .irq = QORIQ_IRQ_DUART, + .irq = QORIQ_IRQ_DUART_1, .initial_baud = BSP_CONSOLE_BAUD }; #endif diff --git a/c/src/lib/libbsp/powerpc/qoriq/console/uart-bridge-master.c b/c/src/lib/libbsp/powerpc/qoriq/console/uart-bridge-master.c index 41ad51779b..588e0a42ad 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/console/uart-bridge-master.c +++ b/c/src/lib/libbsp/powerpc/qoriq/console/uart-bridge-master.c @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2011-2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/bsp.h b/c/src/lib/libbsp/powerpc/qoriq/include/bsp.h index 08760607b5..c0904687f9 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/qoriq/include/bsp.h @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -37,6 +37,16 @@ extern "C" { #define BSP_FEATURE_IRQ_EXTENSION +#define QORIQ_CHIP(alpha, num) ((alpha) * 10000 + (num)) + +#define QORIQ_CHIP_P1020 QORIQ_CHIP('P', 1020) + +#define QORIQ_CHIP_T2080 QORIQ_CHIP('T', 2080) + +#define QORIQ_CHIP_T4240 QORIQ_CHIP('T', 4240) + +#define QORIQ_CHIP_IS_T_VARIANT(variant) ((variant) / 10000 == 'T') + extern unsigned BSP_bus_frequency; struct rtems_bsdnet_ifconfig; diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/irq.h b/c/src/lib/libbsp/powerpc/qoriq/include/irq.h index 3464028560..7f3085732a 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/include/irq.h +++ b/c/src/lib/libbsp/powerpc/qoriq/include/irq.h @@ -7,10 +7,10 @@ */ /* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH - * Obere Lagerstr. 30 + * Dornierstr. 4 * 82178 Puchheim * Germany * <rtems@embedded-brains.de> @@ -23,7 +23,7 @@ #ifndef LIBBSP_POWERPC_QORIQ_IRQ_H #define LIBBSP_POWERPC_QORIQ_IRQ_H -#include <rtems.h> +#include <bsp.h> #include <rtems/irq.h> #include <rtems/irq-extension.h> @@ -31,6 +31,113 @@ extern "C" { #endif /* __cplusplus */ +#define QORIQ_IRQ_ERROR 0 + +#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) + +#define QORIQ_IRQ_PCI_EXPRESS_1 4 +#define QORIQ_IRQ_PCI_EXPRESS_2 5 +#define QORIQ_IRQ_PCI_EXPRESS_3 6 +#define QORIQ_IRQ_PCI_EXPRESS_4 7 +#define QORIQ_IRQ_PAMU 8 +#define QORIQ_IRQ_IFC 9 +#define QORIQ_IRQ_DMA_CHANNEL_1_1 12 +#define QORIQ_IRQ_DMA_CHANNEL_1_2 13 +#define QORIQ_IRQ_DMA_CHANNEL_1_3 14 +#define QORIQ_IRQ_DMA_CHANNEL_1_4 15 +#define QORIQ_IRQ_DMA_CHANNEL_2_1 16 +#define QORIQ_IRQ_DMA_CHANNEL_2_2 17 +#define QORIQ_IRQ_DMA_CHANNEL_2_3 18 +#define QORIQ_IRQ_DMA_CHANNEL_2_4 19 +#define QORIQ_IRQ_DUART_1 20 +#define QORIQ_IRQ_DUART_2 21 +#define QORIQ_IRQ_DUARL_I2C_1 22 +#define QORIQ_IRQ_DUARL_I2C_2 23 +#define QORIQ_IRQ_PCI_EXPRESS_1_INTA 24 +#define QORIQ_IRQ_PCI_EXPRESS_2_INTA 25 +#define QORIQ_IRQ_PCI_EXPRESS_3_INTA 26 +#define QORIQ_IRQ_PCI_EXPRESS_4_INTA 27 +#define QORIQ_IRQ_USB_1 28 +#define QORIQ_IRQ_USB_2 29 +#define QORIQ_IRQ_ESDHC 32 +#define QORIQ_IRQ_PERF_MON 36 +#define QORIQ_IRQ_ESPI 37 +#define QORIQ_IRQ_GPIO_2 38 +#define QORIQ_IRQ_GPIO_1 39 +#define QORIQ_IRQ_SATA_1 52 +#define QORIQ_IRQ_SATA_2 53 +#define QORIQ_IRQ_DMA_CHANNEL_1_5 60 +#define QORIQ_IRQ_DMA_CHANNEL_1_6 61 +#define QORIQ_IRQ_DMA_CHANNEL_1_7 62 +#define QORIQ_IRQ_DMA_CHANNEL_1_8 63 +#define QORIQ_IRQ_DMA_CHANNEL_2_5 64 +#define QORIQ_IRQ_DMA_CHANNEL_2_6 65 +#define QORIQ_IRQ_DMA_CHANNEL_2_7 66 +#define QORIQ_IRQ_DMA_CHANNEL_2_8 67 +#define QORIQ_IRQ_EVENT_PROC_UNIT_1 68 +#define QORIQ_IRQ_EVENT_PROC_UNIT_2 69 +#define QORIQ_IRQ_GPIO_3 70 +#define QORIQ_IRQ_GPIO_4 71 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_1 72 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_2 73 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_3 74 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_4 75 +#define QORIQ_IRQ_SEC_5_2_GLOBAL_ERROR 76 +#define QORIQ_IRQ_SEC_MON 77 +#define QORIQ_IRQ_EVENT_PROC_UNIT_3 78 +#define QORIQ_IRQ_EVENT_PROC_UNIT_4 79 +#define QORIQ_IRQ_FRAME_MGR 80 +#define QORIQ_IRQ_MDIO_1 84 +#define QORIQ_IRQ_MDIO_2 85 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_0 88 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_0 89 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_1 90 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_1 91 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_2 92 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_2 93 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_3 94 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_3 95 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_4 96 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_4 97 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_5 98 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_5 99 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_6 100 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_6 101 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_7 102 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_7 103 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_8 104 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_8 105 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_9 106 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_9 107 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_10 109 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_10 109 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_11 110 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_11 111 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_12 112 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_12 113 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_13 114 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_13 115 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_14 116 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_14 117 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_15 118 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_15 119 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_16 120 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_16 121 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_17 122 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_17 123 +#define QORIQ_IRQ_DMA_CHANNEL_3_1 240 +#define QORIQ_IRQ_DMA_CHANNEL_3_2 241 +#define QORIQ_IRQ_DMA_CHANNEL_3_3 242 +#define QORIQ_IRQ_DMA_CHANNEL_3_4 243 +#define QORIQ_IRQ_DMA_CHANNEL_3_4 244 +#define QORIQ_IRQ_DMA_CHANNEL_3_5 245 +#define QORIQ_IRQ_DMA_CHANNEL_3_6 246 +#define QORIQ_IRQ_DMA_CHANNEL_3_8 247 + +#define QORIQ_IRQ_EXT_BASE 128 + +#else /* QORIQ_CHIP_VARIANT */ + /** * @defgroup QoriqInterruptP1020 QorIQ - P1020 Internal Interrupt Sources * @@ -41,7 +148,6 @@ extern "C" { * @{ */ -#define QORIQ_IRQ_ERROR 0 #define QORIQ_IRQ_ETSEC_TX_1_GROUP_1 1 #define QORIQ_IRQ_ETSEC_RX_1_GROUP_1 2 #define QORIQ_IRQ_ETSEC_ER_1_GROUP_1 8 @@ -107,7 +213,7 @@ extern "C" { #define QORIQ_IRQ_ETSEC_TX_2 19 #define QORIQ_IRQ_ETSEC_RX_2 20 #define QORIQ_IRQ_ETSEC_ER_2 24 -#define QORIQ_IRQ_DUART 26 +#define QORIQ_IRQ_DUART_1 26 #define QORIQ_IRQ_I2C 27 #define QORIQ_IRQ_PERFORMANCE_MONITOR 28 #define QORIQ_IRQ_SECURITY_1 29 @@ -126,6 +232,10 @@ extern "C" { /** @} */ +#define QORIQ_IRQ_EXT_BASE 64 + +#endif /* QORIQ_CHIP_VARIANT */ + /** * @defgroup QoriqInterruptExternal QorIQ - External Interrupt Sources * @@ -136,7 +246,6 @@ extern "C" { * @{ */ -#define QORIQ_IRQ_EXT_BASE 64 #define QORIQ_IRQ_EXT_0 (QORIQ_IRQ_EXT_BASE + 0) #define QORIQ_IRQ_EXT_1 (QORIQ_IRQ_EXT_BASE + 1) #define QORIQ_IRQ_EXT_2 (QORIQ_IRQ_EXT_BASE + 2) diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/mmu.h b/c/src/lib/libbsp/powerpc/qoriq/include/mmu.h index 0215227f30..f08cc43384 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/include/mmu.h +++ b/c/src/lib/libbsp/powerpc/qoriq/include/mmu.h @@ -7,10 +7,10 @@ */ /* - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH - * Obere Lagerstr. 30 + * Dornierstr. 4 * 82178 Puchheim * Germany * <rtems@embedded-brains.de> @@ -26,6 +26,8 @@ #include <stdint.h> #include <stdbool.h> +#include <bspopts.h> + #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ @@ -40,10 +42,8 @@ extern "C" { * @{ */ -#define QORIQ_MMU_ENTRY_COUNT 32 - #define QORIQ_MMU_MIN_POWER 12 -#define QORIQ_MMU_MAX_POWER 32 +#define QORIQ_MMU_MAX_POWER 30 #define QORIQ_MMU_POWER_STEP 2 typedef struct { @@ -57,7 +57,7 @@ typedef struct { typedef struct { int count; - qoriq_mmu_entry entries [QORIQ_MMU_ENTRY_COUNT]; + qoriq_mmu_entry entries [QORIQ_TLB1_ENTRY_COUNT]; } qoriq_mmu_context; void qoriq_mmu_context_init(qoriq_mmu_context *self); diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/qoriq.h b/c/src/lib/libbsp/powerpc/qoriq/include/qoriq.h index e56c30fc16..0bacc54463 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/include/qoriq.h +++ b/c/src/lib/libbsp/powerpc/qoriq/include/qoriq.h @@ -7,10 +7,10 @@ */ /* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH - * Obere Lagerstr. 30 + * Dornierstr. 4 * 82178 Puchheim * Germany * <rtems@embedded-brains.de> @@ -23,6 +23,7 @@ #ifndef LIBBSP_POWERPC_QORIQ_QORIQ_H #define LIBBSP_POWERPC_QORIQ_QORIQ_H +#include <bsp.h> #include <bsp/tsec.h> #include <bsp/utility.h> @@ -34,6 +35,188 @@ extern "C" { #define QORIQ_RESERVE(a, b) uint8_t reserved_ ## b [b - a] typedef struct { + uint32_t reg; + QORIQ_FILL(0x00000, 0x00010, uint32_t); +} qoriq_pic_reg; + +typedef struct { + uint32_t ccr; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t bcr; + QORIQ_FILL(0x00010, 0x00020, uint32_t); + uint32_t vpr; + QORIQ_FILL(0x00020, 0x00030, uint32_t); + uint32_t dr; + QORIQ_FILL(0x00030, 0x00040, uint32_t); +} qoriq_pic_global_timer; + +#define GTCCR_TOG BSP_BBIT32(0) +#define GTCCR_COUNT_GET(reg) BSP_BFLD32GET(reg, 1, 31) + +#define GTBCR_CI BSP_BBIT32(0) +#define GTBCR_COUNT(val) BSP_BFLD32(val, 1, 31) +#define GTBCR_COUNT_GET(reg) BSP_BFLD32GET(reg, 1, 31) +#define GTBCR_COUNT_SET(reg, val) BSP_BFLD32SET(reg, val, 1, 31) + +typedef struct { + uint32_t misc; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t internal [2]; + QORIQ_FILL(0x00010, 0x00020, uint32_t [2]); +} qoriq_pic_bit_field; + +typedef struct { + uint32_t vpr; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t dr; + QORIQ_FILL(0x00010, 0x00020, uint32_t); +} qoriq_pic_src_cfg; + +typedef struct { + QORIQ_RESERVE(0x00000, 0x00040); + qoriq_pic_reg ipidr [4]; + uint32_t ctpr; + QORIQ_FILL(0x00080, 0x00090, uint32_t); + uint32_t whoami; + QORIQ_FILL(0x00090, 0x000a0, uint32_t); + uint32_t iack; + QORIQ_FILL(0x000a0, 0x000b0, uint32_t); + uint32_t eoi; + QORIQ_FILL(0x000b0, 0x01000, uint32_t); +} qoriq_pic_per_cpu; + +typedef struct { + uint32_t brr1; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t brr2; + QORIQ_FILL(0x00010, 0x00040, uint32_t); + qoriq_pic_reg ipidr [4]; + uint32_t ctpr; + QORIQ_FILL(0x00080, 0x00090, uint32_t); + uint32_t whoami; + QORIQ_FILL(0x00090, 0x000a0, uint32_t); + uint32_t iack; + QORIQ_FILL(0x000a0, 0x000b0, uint32_t); + uint32_t eoi; + QORIQ_FILL(0x000b0, 0x01000, uint32_t); + uint32_t frr; + QORIQ_FILL(0x01000, 0x01020, uint32_t); + uint32_t gcr; + QORIQ_FILL(0x01020, 0x01080, uint32_t); + uint32_t vir; + QORIQ_FILL(0x01080, 0x01090, uint32_t); + uint32_t pir; + QORIQ_FILL(0x01090, 0x010a0, uint32_t); + qoriq_pic_reg ipivpr [4]; + uint32_t svr; + QORIQ_FILL(0x010e0, 0x010f0, uint32_t); + uint32_t tfrra; + QORIQ_FILL(0x010f0, 0x01100, uint32_t); + qoriq_pic_global_timer gta [4]; + QORIQ_RESERVE(0x01200, 0x01300); + uint32_t tcra; + QORIQ_FILL(0x01300, 0x01308, uint32_t); + uint32_t erqsr; + QORIQ_FILL(0x01308, 0x01310, uint32_t); + qoriq_pic_bit_field irqsr; + qoriq_pic_bit_field cisr; + qoriq_pic_bit_field pm [4]; + QORIQ_RESERVE(0x013d0, 0x01400); + qoriq_pic_reg msgr03 [4]; + QORIQ_RESERVE(0x01440, 0x01500); + uint32_t mer03; + QORIQ_FILL(0x01500, 0x01510, uint32_t); + uint32_t msr03; + QORIQ_FILL(0x01510, 0x01600, uint32_t); + qoriq_pic_reg msir [8]; + QORIQ_RESERVE(0x01680, 0x01720); + uint32_t msisr; + QORIQ_FILL(0x01720, 0x01740, uint32_t); + uint32_t msiir; + QORIQ_FILL(0x01740, 0x020f0, uint32_t); + uint32_t tfrrb; + QORIQ_FILL(0x020f0, 0x02100, uint32_t); + qoriq_pic_global_timer gtb [4]; + QORIQ_RESERVE(0x02200, 0x02300); + uint32_t tcrb; + QORIQ_FILL(0x02300, 0x02400, uint32_t); + qoriq_pic_reg msgr47 [4]; + QORIQ_RESERVE(0x02440, 0x02500); + uint32_t mer47; + QORIQ_FILL(0x02500, 0x02510, uint32_t); + uint32_t msr47; + QORIQ_FILL(0x02510, 0x10000, uint32_t); + qoriq_pic_src_cfg ei [12]; + QORIQ_RESERVE(0x10180, 0x10200); + qoriq_pic_src_cfg ii [64]; + QORIQ_RESERVE(0x10a00, 0x11600); + qoriq_pic_src_cfg mi [8]; + QORIQ_RESERVE(0x11700, 0x11c00); + qoriq_pic_src_cfg msi [8]; + QORIQ_RESERVE(0x11d00, 0x20000); + qoriq_pic_per_cpu per_cpu [2]; +} qoriq_pic; + +#define GTTCR_ROVR(val) BSP_BFLD32(val, 5, 7) +#define GTTCR_ROVR_GET(reg) BSP_BFLD32GET(reg, 5, 7) +#define GTTCR_ROVR_SET(reg, val) BSP_BFLD32SET(reg, val, 5, 7) +#define GTTCR_RTM BSP_BBIT32(15) +#define GTTCR_CLKR(val) BSP_BFLD32(val, 22, 23) +#define GTTCR_CLKR_GET(reg) BSP_BFLD32GET(reg, 22, 23) +#define GTTCR_CLKR_SET(reg, val) BSP_BFLD32SET(reg, val, 22, 23) +#define GTTCR_CASC(val) BSP_BFLD32(val, 29, 31) +#define GTTCR_CASC_GET(reg) BSP_BFLD32GET(reg, 29, 31) +#define GTTCR_CASC_SET(reg, val) BSP_BFLD32SET(reg, val, 29, 31) + +typedef struct { +} qoriq_uart; + +#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) + +typedef struct { + uint32_t ccsrbarh; + uint32_t ccsrbarl; + uint32_t ccsrar; + uint32_t altcbarh; + uint32_t altcbarl; + uint32_t altcar; + uint32_t bstrh; + uint32_t bstrl; + uint32_t bstar; +} qoriq_lcc; + +#define LCC_BSTAR_EN BSP_BBIT32(0) + +typedef struct { + uint32_t lawbarh; + uint32_t lawbarl; + uint32_t lawar; + uint32_t reserved_0xc; +} qoriq_law; + +typedef struct { + qoriq_lcc lcc; + QORIQ_FILL(0x000000, 0x000c00, qoriq_lcc); + qoriq_law law [32]; + QORIQ_FILL(0x000c00, 0x001000, qoriq_law [32]); + QORIQ_RESERVE(0x001000, 0x040000); + qoriq_pic pic; + QORIQ_FILL(0x040000, 0x070000, qoriq_pic); + QORIQ_RESERVE(0x070000, 0x11c500); + qoriq_uart uart_0; + QORIQ_FILL(0x11c500, 0x11c600, qoriq_uart); + qoriq_uart uart_1; + QORIQ_FILL(0x11c600, 0x11d500, qoriq_uart); + qoriq_uart uart_2; + QORIQ_FILL(0x11d500, 0x11d600, qoriq_uart); + qoriq_uart uart_3; + QORIQ_FILL(0x11d600, 0x11e000, qoriq_uart); + QORIQ_RESERVE(0x11e000, 0x2000000); +} qoriq_ccsr; + +#else /* QORIQ_CHIP_VARIANT */ + +typedef struct { uint32_t ccsrbar; uint32_t reserved_0; uint32_t altcbar; @@ -90,9 +273,6 @@ typedef struct { } qoriq_i2c; typedef struct { -} qoriq_uart; - -typedef struct { } qoriq_local_bus; typedef struct { @@ -196,140 +376,6 @@ typedef struct { } qoriq_sec; typedef struct { - uint32_t reg; - QORIQ_FILL(0x00000, 0x00010, uint32_t); -} qoriq_pic_reg; - -typedef struct { - uint32_t ccr; - QORIQ_FILL(0x00000, 0x00010, uint32_t); - uint32_t bcr; - QORIQ_FILL(0x00010, 0x00020, uint32_t); - uint32_t vpr; - QORIQ_FILL(0x00020, 0x00030, uint32_t); - uint32_t dr; - QORIQ_FILL(0x00030, 0x00040, uint32_t); -} qoriq_pic_global_timer; - -#define GTCCR_TOG BSP_BBIT32(0) -#define GTCCR_COUNT_GET(reg) BSP_BFLD32GET(reg, 1, 31) - -#define GTBCR_CI BSP_BBIT32(0) -#define GTBCR_COUNT(val) BSP_BFLD32(val, 1, 31) -#define GTBCR_COUNT_GET(reg) BSP_BFLD32GET(reg, 1, 31) -#define GTBCR_COUNT_SET(reg, val) BSP_BFLD32SET(reg, val, 1, 31) - -typedef struct { - uint32_t misc; - QORIQ_FILL(0x00000, 0x00010, uint32_t); - uint32_t internal [2]; - QORIQ_FILL(0x00010, 0x00020, uint32_t [2]); -} qoriq_pic_bit_field; - -typedef struct { - uint32_t vpr; - QORIQ_FILL(0x00000, 0x00010, uint32_t); - uint32_t dr; - QORIQ_FILL(0x00010, 0x00020, uint32_t); -} qoriq_pic_src_cfg; - -typedef struct { - QORIQ_RESERVE(0x00000, 0x00040); - qoriq_pic_reg ipidr [4]; - uint32_t ctpr; - QORIQ_FILL(0x00080, 0x00090, uint32_t); - uint32_t whoami; - QORIQ_FILL(0x00090, 0x000a0, uint32_t); - uint32_t iack; - QORIQ_FILL(0x000a0, 0x000b0, uint32_t); - uint32_t eoi; - QORIQ_FILL(0x000b0, 0x01000, uint32_t); -} qoriq_pic_per_cpu; - -typedef struct { - uint32_t brr1; - QORIQ_FILL(0x00000, 0x00010, uint32_t); - uint32_t brr2; - QORIQ_FILL(0x00010, 0x00040, uint32_t); - qoriq_pic_reg ipidr [4]; - uint32_t ctpr; - QORIQ_FILL(0x00080, 0x00090, uint32_t); - uint32_t whoami; - QORIQ_FILL(0x00090, 0x000a0, uint32_t); - uint32_t iack; - QORIQ_FILL(0x000a0, 0x000b0, uint32_t); - uint32_t eoi; - QORIQ_FILL(0x000b0, 0x01000, uint32_t); - uint32_t frr; - QORIQ_FILL(0x01000, 0x01020, uint32_t); - uint32_t gcr; - QORIQ_FILL(0x01020, 0x01080, uint32_t); - uint32_t vir; - QORIQ_FILL(0x01080, 0x01090, uint32_t); - uint32_t pir; - QORIQ_FILL(0x01090, 0x010a0, uint32_t); - qoriq_pic_reg ipivpr [4]; - uint32_t svr; - QORIQ_FILL(0x010e0, 0x010f0, uint32_t); - uint32_t tfrra; - QORIQ_FILL(0x010f0, 0x01100, uint32_t); - qoriq_pic_global_timer gta [4]; - QORIQ_RESERVE(0x01200, 0x01300); - uint32_t tcra; - QORIQ_FILL(0x01300, 0x01308, uint32_t); - uint32_t erqsr; - QORIQ_FILL(0x01308, 0x01310, uint32_t); - qoriq_pic_bit_field irqsr; - qoriq_pic_bit_field cisr; - qoriq_pic_bit_field pm [4]; - QORIQ_RESERVE(0x013d0, 0x01400); - qoriq_pic_reg msgr03 [4]; - QORIQ_RESERVE(0x01440, 0x01500); - uint32_t mer03; - QORIQ_FILL(0x01500, 0x01510, uint32_t); - uint32_t msr03; - QORIQ_FILL(0x01510, 0x01600, uint32_t); - qoriq_pic_reg msir [8]; - QORIQ_RESERVE(0x01680, 0x01720); - uint32_t msisr; - QORIQ_FILL(0x01720, 0x01740, uint32_t); - uint32_t msiir; - QORIQ_FILL(0x01740, 0x020f0, uint32_t); - uint32_t tfrrb; - QORIQ_FILL(0x020f0, 0x02100, uint32_t); - qoriq_pic_global_timer gtb [4]; - QORIQ_RESERVE(0x02200, 0x02300); - uint32_t tcrb; - QORIQ_FILL(0x02300, 0x02400, uint32_t); - qoriq_pic_reg msgr47 [4]; - QORIQ_RESERVE(0x02440, 0x02500); - uint32_t mer47; - QORIQ_FILL(0x02500, 0x02510, uint32_t); - uint32_t msr47; - QORIQ_FILL(0x02510, 0x10000, uint32_t); - qoriq_pic_src_cfg ei [12]; - QORIQ_RESERVE(0x10180, 0x10200); - qoriq_pic_src_cfg ii [64]; - QORIQ_RESERVE(0x10a00, 0x11600); - qoriq_pic_src_cfg mi [8]; - QORIQ_RESERVE(0x11700, 0x11c00); - qoriq_pic_src_cfg msi [8]; - QORIQ_RESERVE(0x11d00, 0x20000); - qoriq_pic_per_cpu per_cpu [2]; -} qoriq_pic; - -#define GTTCR_ROVR(val) BSP_BFLD32(val, 5, 7) -#define GTTCR_ROVR_GET(reg) BSP_BFLD32GET(reg, 5, 7) -#define GTTCR_ROVR_SET(reg, val) BSP_BFLD32SET(reg, val, 5, 7) -#define GTTCR_RTM BSP_BBIT32(15) -#define GTTCR_CLKR(val) BSP_BFLD32(val, 22, 23) -#define GTTCR_CLKR_GET(reg) BSP_BFLD32GET(reg, 22, 23) -#define GTTCR_CLKR_SET(reg, val) BSP_BFLD32SET(reg, val, 22, 23) -#define GTTCR_CASC(val) BSP_BFLD32(val, 29, 31) -#define GTTCR_CASC_GET(reg) BSP_BFLD32GET(reg, 29, 31) -#define GTTCR_CASC_SET(reg, val) BSP_BFLD32SET(reg, val, 29, 31) - -typedef struct { } qoriq_serial_rapid_io; typedef struct { @@ -441,6 +487,8 @@ typedef struct { QORIQ_FILL(0xf0000, 0x100000, qoriq_boot_rom); } qoriq_ccsr; +#endif /* QORIQ_CHIP_VARIANT */ + extern volatile qoriq_ccsr qoriq; #ifdef __cplusplus diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/tm27.h b/c/src/lib/libbsp/powerpc/qoriq/include/tm27.h index cc35487ca9..46264b7e67 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/include/tm27.h +++ b/c/src/lib/libbsp/powerpc/qoriq/include/tm27.h @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/u-boot-config.h b/c/src/lib/libbsp/powerpc/qoriq/include/u-boot-config.h index 5a34906ecd..3e6fa90b55 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/include/u-boot-config.h +++ b/c/src/lib/libbsp/powerpc/qoriq/include/u-boot-config.h @@ -1,8 +1,8 @@ /* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH - * Obere Lagerstr. 30 + * Dornierstr. 4 * 82178 Puchheim * Germany * <rtems@embedded-brains.de> @@ -15,6 +15,12 @@ #ifndef LIBBSP_POWERPC_QORIQ_U_BOOT_CONFIG_H #define LIBBSP_POWERPC_QORIQ_U_BOOT_CONFIG_H +#include <bspopts.h> + +#define U_BOOT_BOARD_INFO_TEXT_SECTION __attribute__((section(".bsp_start_text"))) + +#define U_BOOT_BOARD_INFO_DATA_SECTION __attribute__((section(".bsp_start_data"))) + #define CONFIG_E500 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/uart-bridge.h b/c/src/lib/libbsp/powerpc/qoriq/include/uart-bridge.h index cd342ffcb6..97e6553b7c 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/include/uart-bridge.h +++ b/c/src/lib/libbsp/powerpc/qoriq/include/uart-bridge.h @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2011-2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 diff --git a/c/src/lib/libbsp/powerpc/qoriq/irq/irq.c b/c/src/lib/libbsp/powerpc/qoriq/irq/irq.c index 8978b46aa7..57de87bf65 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/qoriq/irq/irq.c @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 diff --git a/c/src/lib/libbsp/powerpc/qoriq/make/custom/qoriq_t2080rdb.cfg b/c/src/lib/libbsp/powerpc/qoriq/make/custom/qoriq_t2080rdb.cfg new file mode 100644 index 0000000000..a373f32787 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/qoriq/make/custom/qoriq_t2080rdb.cfg @@ -0,0 +1,12 @@ +# Config file for T2080RDB + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = powerpc + +RTEMS_CPU_MODEL = qoriq + +CPU_CFLAGS = -mcpu=e6500 -m32 -msdata=sysv -fno-common \ + -D__ppc_generic + +CFLAGS_OPTIMIZE_V = -Os -g diff --git a/c/src/lib/libbsp/powerpc/qoriq/make/custom/qoriq_t4240rdb.cfg b/c/src/lib/libbsp/powerpc/qoriq/make/custom/qoriq_t4240rdb.cfg new file mode 100644 index 0000000000..ad8c294a45 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/qoriq/make/custom/qoriq_t4240rdb.cfg @@ -0,0 +1,3 @@ +# Config file for T4240RDB + +include $(RTEMS_ROOT)/make/custom/qoriq_t2080rdb.cfg diff --git a/c/src/lib/libbsp/powerpc/qoriq/network/network.c b/c/src/lib/libbsp/powerpc/qoriq/network/network.c index 5ac9c2987a..bbcfc8e204 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/network/network.c +++ b/c/src/lib/libbsp/powerpc/qoriq/network/network.c @@ -7,10 +7,10 @@ */ /* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH - * Obere Lagerstr. 30 + * Dornierstr. 4 * 82178 Puchheim * Germany * <rtems@embedded-brains.de> @@ -36,6 +36,8 @@ #include <bsp/u-boot.h> #include <bsp/qoriq.h> +#if QORIQ_CHIP_VARIANT == QORIQ_CHIP_P1020 + int BSP_tsec_attach( struct rtems_bsdnet_ifconfig *config, int attaching @@ -131,3 +133,5 @@ int BSP_tsec_attach( return tsec_driver_attach_detach(config, attaching); } + +#endif /* QORIQ_CHIP_VARIANT */ diff --git a/c/src/lib/libbsp/powerpc/qoriq/preinstall.am b/c/src/lib/libbsp/powerpc/qoriq/preinstall.am index 4a50d5bbbd..484821b5d5 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/preinstall.am +++ b/c/src/lib/libbsp/powerpc/qoriq/preinstall.am @@ -81,6 +81,10 @@ $(PROJECT_INCLUDE)/bsp/u-boot-board-info.h: ../shared/include/u-boot-board-info. $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/u-boot-board-info.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/u-boot-board-info.h +$(PROJECT_INCLUDE)/bsp/u-boot-generic-board-info.h: ../shared/include/u-boot-generic-board-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/u-boot-generic-board-info.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/u-boot-generic-board-info.h + $(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h @@ -145,3 +149,11 @@ $(PROJECT_LIB)/linkcmds.qoriq_p1020rdb: startup/linkcmds.qoriq_p1020rdb $(PROJEC $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.qoriq_p1020rdb PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.qoriq_p1020rdb +$(PROJECT_LIB)/linkcmds.qoriq_t2080rdb: startup/linkcmds.qoriq_t2080rdb $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.qoriq_t2080rdb +PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.qoriq_t2080rdb + +$(PROJECT_LIB)/linkcmds.qoriq_t4240rdb: startup/linkcmds.qoriq_t4240rdb $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.qoriq_t4240rdb +PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.qoriq_t4240rdb + diff --git a/c/src/lib/libbsp/powerpc/qoriq/start/start.S b/c/src/lib/libbsp/powerpc/qoriq/start/start.S index b03fb4483d..6b2187c1be 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/start/start.S +++ b/c/src/lib/libbsp/powerpc/qoriq/start/start.S @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -20,7 +20,7 @@ * http://www.rtems.org/license/LICENSE. */ -#include <rtems/asm.h> +#include <rtems/score/percpu.h> #include <bspopts.h> @@ -29,26 +29,25 @@ #include <bsp/vectors.h> #define FIRST_TLB 0 -#define SCRATCH_TLB 15 +#define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1 #define INITIAL_MSR r14 -#define UBOOT_BOARD_INFO r15 .globl _start #ifdef RTEMS_SMP - .globl _start_core_1 +#if QORIQ_THREAD_COUNT > 1 + .globl _start_thread +#endif + .globl _start_secondary_processor #endif .globl bsp_exc_vector_base .section ".bsp_start_text", "ax" _start: - /* Reset time base */ - li r0, 0 - mtspr TBWU, r0 - mtspr TBWL, r0 + bl .Linit #ifdef HAS_UBOOT - mr UBOOT_BOARD_INFO, r3 + bl bsp_uboot_copy_board_info #endif /* HAS_UBOOT */ /* Initial MMU setup */ @@ -67,13 +66,9 @@ _start: ori r0, INITIAL_MSR, MSR_IS | MSR_DS mtmsr r0 - /* SPEFSCR initialization */ - LWI r0, QORIQ_INITIAL_SPEFSCR - mtspr FSL_EIS_SPEFSCR, r0 - /* Initialize start stack */ - LWI r1, start_stack_end - subi r1, r1, 16 + LWI r1, start_stack_end - PPC_MINIMUM_STACK_FRAME_SIZE + clrrwi r1, r1, PPC_STACK_ALIGN_POWER li r0, 0 stw r0, 0(r1) @@ -81,39 +76,39 @@ _start: LWI r3, bsp_section_fast_text_begin LWI r4, bsp_section_fast_text_load_begin LWI r5, bsp_section_fast_text_size - bl copy + bl .Lcopy /* Copy read-only data */ LWI r3, bsp_section_rodata_begin LWI r4, bsp_section_rodata_load_begin LWI r5, bsp_section_rodata_size - bl copy + bl .Lcopy /* Copy fast data */ LWI r3, bsp_section_fast_data_begin LWI r4, bsp_section_fast_data_load_begin LWI r5, bsp_section_fast_data_size - bl copy + bl .Lcopy /* Copy data */ LWI r3, bsp_section_data_begin LWI r4, bsp_section_data_load_begin LWI r5, bsp_section_data_size - bl copy + bl .Lcopy /* NULL pointer access protection (only core 0 has to do this) */ mfspr r3, BOOKE_PIR cmpwi r3, 0 - bne null_area_setup_done + bne .Lnull_area_setup_done LWI r3, bsp_section_start_begin srawi r3, r3, 2 mtctr r3 li r3, -4 LWI r4, 0x44000002 -null_area_setup_loop: +.Lnull_area_setup_loop: stwu r4, 4(r3) - bdnz null_area_setup_loop -null_area_setup_done: + bdnz .Lnull_area_setup_loop +.Lnull_area_setup_done: /* Configure MMU */ li r3, FIRST_TLB @@ -133,21 +128,6 @@ null_area_setup_done: LWI r4, bsp_section_bss_size bl bsp_start_zero -#ifdef HAS_UBOOT - li r3, SCRATCH_TLB - li r4, 0 - li r5, 0 - li r6, FSL_EIS_MAS3_SR - li r7, 0 - mr r8, UBOOT_BOARD_INFO - li r9, 1 - bl qoriq_tlb1_write - mr r3, UBOOT_BOARD_INFO - bl bsp_uboot_copy_board_info - li r3, SCRATCH_TLB - bl qoriq_tlb1_invalidate -#endif /* HAS_UBOOT */ - /* Set up EABI and SYSV environment */ bl __eabi @@ -156,24 +136,63 @@ null_area_setup_done: bl boot_card -twiddle: - b twiddle - -copy: +.Lcopy: cmpw r3, r4 beqlr b memcpy -#ifdef RTEMS_SMP -_start_core_1: - + /* Do not use r3 here, since this could be the U-Boot board info */ +.Linit: /* Reset time base */ li r0, 0 mtspr TBWU, r0 mtspr TBWL, r0 + /* Disable decrementer */ + mfspr r0, BOOKE_TCR + LWI r4, BOOKE_TCR_DIE + andc r0, r0, r4 + mtspr BOOKE_TCR, r0 + +#ifdef QORIQ_INITIAL_SPEFSCR + /* SPEFSCR initialization */ + LWI r0, QORIQ_INITIAL_SPEFSCR + mtspr FSL_EIS_SPEFSCR, r0 +#endif + + /* Set small-data anchors */ + LA r2, _SDA2_BASE_ + LA r13, _SDA_BASE_ + + blr + +#ifdef RTEMS_SMP +#if QORIQ_THREAD_COUNT > 1 +_start_thread: + /* Adjust PIR */ + mfspr r0, BOOKE_PIR + srawi r0, r0, 2 + ori r0, r0, 1 + mtspr BOOKE_PIR, r0 + + bl .Linit + + /* Initialize start stack */ + GET_SELF_CPU_CONTROL r3 + lwz r3, PER_CPU_INTERRUPT_STACK_HIGH(r3) + subi r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE + clrrwi r1, r1, PPC_STACK_ALIGN_POWER + li r0, 0 + stw r0, 0(r1) + + b qoriq_start_thread +#endif +_start_secondary_processor: + + bl .Linit + /* Get start stack */ - subi r1, r3, 16 + mr r1, r3 /* Initial MMU setup */ bl qoriq_tlb1_ts_0_only @@ -191,11 +210,9 @@ _start_core_1: ori r0, INITIAL_MSR, MSR_IS | MSR_DS mtmsr r0 - /* SPEFSCR initialization */ - LWI r0, QORIQ_INITIAL_SPEFSCR - mtspr FSL_EIS_SPEFSCR, r0 - /* Initialize start stack */ + subi r1, r1, PPC_MINIMUM_STACK_FRAME_SIZE + clrrwi r1, r1, PPC_STACK_ALIGN_POWER li r0, 0 stw r0, 0(r1) @@ -207,13 +224,7 @@ _start_core_1: li r3, SCRATCH_TLB bl qoriq_tlb1_invalidate - /* Set small-data anchors */ - LA r2, _SDA2_BASE_ - LA r13, _SDA_BASE_ - b bsp_start_on_secondary_processor - - b twiddle #endif /* RTEMS_SMP */ /* Exception vector prologues area */ diff --git a/c/src/lib/libbsp/powerpc/qoriq/startup/bspsmp.c b/c/src/lib/libbsp/powerpc/qoriq/startup/bspsmp.c index c60230a8f4..80764fec2c 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/startup/bspsmp.c +++ b/c/src/lib/libbsp/powerpc/qoriq/startup/bspsmp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -12,14 +12,13 @@ * http://www.rtems.org/license/LICENSE. */ -#include <assert.h> - #include <rtems/score/smpimpl.h> #include <libcpu/powerpc-utility.h> #include <bsp.h> #include <bsp/mmu.h> +#include <bsp/fatal.h> #include <bsp/qoriq.h> #include <bsp/vectors.h> #include <bsp/bootcard.h> @@ -28,19 +27,17 @@ LINKER_SYMBOL(bsp_exc_vector_base); -void _start_core_1(void); - -#define CORE_COUNT 2 - -#define ONE_CORE(core) (1 << (core)) +#if QORIQ_THREAD_COUNT > 1 +void _start_thread(void); +#endif -#define ALL_CORES ((1 << CORE_COUNT) - 1) +void _start_secondary_processor(void); #define IPI_INDEX 0 -#define TLB_BEGIN 8 +#define TLB_BEGIN (3 * QORIQ_TLB1_ENTRY_COUNT / 4) -#define TLB_END 16 +#define TLB_END QORIQ_TLB1_ENTRY_COUNT #define TLB_COUNT (TLB_END - TLB_BEGIN) @@ -48,84 +45,76 @@ void _start_core_1(void); * These values can be obtained with the debugger or a look into the * U-Boot sources (arch/powerpc/cpu/mpc85xx/release.S). */ -#if 1 - #define BOOT_BEGIN 0x1fff0000 - #define BOOT_LAST 0x1fffffff - #define SPIN_TABLE (BOOT_BEGIN + 0xf2a0) -#else - #define BOOT_BEGIN 0x3fff0000 - #define BOOT_LAST 0x3fffffff - #define SPIN_TABLE (BOOT_BEGIN + 0xf240) -#endif - -#define TLB_BEGIN 8 - -#define TLB_END 16 - -#define TLB_COUNT (TLB_END - TLB_BEGIN) +#define BOOT_BEGIN U_BOOT_BOOT_PAGE_BEGIN +#define BOOT_LAST U_BOOT_BOOT_PAGE_LAST +#define SPIN_TABLE (BOOT_BEGIN + U_BOOT_BOOT_PAGE_SPIN_OFFSET) typedef struct { uint32_t addr_upper; uint32_t addr_lower; uint32_t r3_upper; uint32_t r3_lower; - uint32_t reserved; + uint32_t reserved_0; uint32_t pir; uint32_t r6_upper; uint32_t r6_lower; + uint32_t reserved_1[8]; } uboot_spin_table; -static uint32_t initial_core_1_stack[4096 / sizeof(uint32_t)]; - -static void mmu_config_undo(void) +#if QORIQ_THREAD_COUNT > 1 +static bool is_started_by_u_boot(uint32_t cpu_index) { - int i = 0; - - for (i = TLB_BEGIN; i < TLB_END; ++i) { - qoriq_tlb1_invalidate(i); - } + return cpu_index % QORIQ_THREAD_COUNT == 0; } -static void release_core_1(void) +void qoriq_start_thread(void) { - const Per_CPU_Control *second_cpu = _Per_CPU_Get_by_index(1); - uboot_spin_table *spin_table = (uboot_spin_table *) SPIN_TABLE; - qoriq_mmu_context mmu_context; - - qoriq_mmu_context_init(&mmu_context); - qoriq_mmu_add( - &mmu_context, - BOOT_BEGIN, - BOOT_LAST, - 0, - 0, - FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW, - 0 + const Per_CPU_Control *cpu_self = _Per_CPU_Get(); + + ppc_exc_initialize_interrupt_stack( + (uintptr_t) cpu_self->interrupt_stack_low, + rtems_configuration_get_interrupt_stack_size() ); - qoriq_mmu_partition(&mmu_context, TLB_COUNT); - qoriq_mmu_write_to_tlb1(&mmu_context, TLB_BEGIN); - spin_table->pir = 1; - spin_table->r3_lower = (uint32_t) second_cpu->interrupt_stack_high; - spin_table->addr_upper = 0; - rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table)); - ppc_synchronize_data(); - spin_table->addr_lower = (uint32_t) _start_core_1; - rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table)); + bsp_interrupt_facility_initialize(); - mmu_config_undo(); + _SMP_Start_multitasking_on_secondary_processor(); } +#endif -void bsp_start_on_secondary_processor(void) +static void start_thread_if_necessary(uint32_t cpu_index_self) { - const Per_CPU_Control *second_cpu = _Per_CPU_Get_by_index(1); +#if QORIQ_THREAD_COUNT > 1 + uint32_t i; + + for (i = 1; i < QORIQ_THREAD_COUNT; ++i) { + uint32_t cpu_index_next = cpu_index_self + i; + + if ( + is_started_by_u_boot(cpu_index_self) + && cpu_index_next < rtems_configuration_get_maximum_processors() + && _SMP_Should_start_processor(cpu_index_next) + ) { + /* Thread Initial Next Instruction Address (INIA) */ + PPC_SET_THREAD_MGMT_REGISTER(321, (uint32_t) _start_thread); + + /* Thread Initial Machine State (IMSR) */ + PPC_SET_THREAD_MGMT_REGISTER(289, QORIQ_INITIAL_MSR); + + /* Thread Enable Set (TENS) */ + PPC_SET_SPECIAL_PURPOSE_REGISTER(438, 1U << i); + } + } +#endif +} - /* Disable decrementer */ - PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE); +void bsp_start_on_secondary_processor(void) +{ + uint32_t cpu_index_self = _SMP_Get_current_processor(); + const Per_CPU_Control *cpu_self = _Per_CPU_Get_by_index(cpu_index_self); - /* Initialize exception handler */ ppc_exc_initialize_with_vector_base( - (uintptr_t) second_cpu->interrupt_stack_low, + (uintptr_t) cpu_self->interrupt_stack_low, rtems_configuration_get_interrupt_stack_size(), bsp_exc_vector_base ); @@ -137,10 +126,9 @@ void bsp_start_on_secondary_processor(void) FSL_EIS_MAS3_SR ); - /* Initialize interrupt support */ bsp_interrupt_facility_initialize(); - bsp_interrupt_vector_enable(QORIQ_IRQ_IPI_0); + start_thread_if_necessary(cpu_index_self); _SMP_Start_multitasking_on_secondary_processor(); } @@ -152,20 +140,78 @@ static void bsp_inter_processor_interrupt(void *arg) uint32_t _CPU_SMP_Initialize(void) { - return CORE_COUNT; + if (rtems_configuration_get_maximum_processors() > 0) { + qoriq_mmu_context mmu_context; + + qoriq_mmu_context_init(&mmu_context); + qoriq_mmu_add( + &mmu_context, + BOOT_BEGIN, + BOOT_LAST, + 0, + 0, + FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW, + 0 + ); + qoriq_mmu_partition(&mmu_context, TLB_COUNT); + qoriq_mmu_write_to_tlb1(&mmu_context, TLB_BEGIN); + } + + start_thread_if_necessary(0); + + return QORIQ_CPU_COUNT; +} + +static void release_processor(uboot_spin_table *spin_table, uint32_t cpu_index) +{ + const Per_CPU_Control *cpu = _Per_CPU_Get_by_index(cpu_index); + + spin_table->pir = cpu_index; + spin_table->r3_lower = (uint32_t) cpu->interrupt_stack_high; + spin_table->addr_upper = 0; + rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table)); + ppc_synchronize_data(); + spin_table->addr_lower = (uint32_t) _start_secondary_processor; + rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table)); } bool _CPU_SMP_Start_processor(uint32_t cpu_index) { - (void) cpu_index; +#if QORIQ_THREAD_COUNT > 1 + if (is_started_by_u_boot(cpu_index)) { + uboot_spin_table *spin_table = + &((uboot_spin_table *) SPIN_TABLE)[cpu_index / 2 - 1]; - release_core_1(); + release_processor(spin_table, cpu_index); + + return true; + } else { + return _SMP_Should_start_processor(cpu_index - 1); + } +#else + uboot_spin_table *spin_table = (uboot_spin_table *) SPIN_TABLE; + + release_processor(spin_table, cpu_index); return true; +#endif +} + +static void mmu_config_undo(void) +{ + int i; + + for (i = TLB_BEGIN; i < TLB_END; ++i) { + qoriq_tlb1_invalidate(i); + } } void _CPU_SMP_Finalize_initialization(uint32_t cpu_count) { + if (rtems_configuration_get_maximum_processors() > 0) { + mmu_config_undo(); + } + if (cpu_count > 1) { rtems_status_code sc; @@ -176,13 +222,13 @@ void _CPU_SMP_Finalize_initialization(uint32_t cpu_count) bsp_inter_processor_interrupt, NULL ); - assert(sc == RTEMS_SUCCESSFUL); + if (sc != RTEMS_SUCCESSFUL) { + bsp_fatal(QORIQ_FATAL_SMP_IPI_HANDLER_INSTALL); + } } } void _CPU_SMP_Send_interrupt(uint32_t target_processor_index) { - uint32_t self = ppc_processor_id(); - qoriq.pic.per_cpu [self].ipidr [IPI_INDEX].reg = - ONE_CORE(target_processor_index); + qoriq.pic.ipidr [IPI_INDEX].reg = 1U << target_processor_index; } diff --git a/c/src/lib/libbsp/powerpc/qoriq/startup/bspstart.c b/c/src/lib/libbsp/powerpc/qoriq/startup/bspstart.c index 364d8af875..9784cbe943 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/qoriq/startup/bspstart.c @@ -87,8 +87,9 @@ void bsp_start(void) /* Initialize some device driver parameters */ #ifdef HAS_UBOOT - BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq; - bsp_clicks_per_usec = bsp_uboot_board_info.bi_busfreq / 8000000; + BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq + / QORIQ_BUS_CLOCK_DIVIDER; + bsp_clicks_per_usec = BSP_bus_frequency / 8000000; rtems_counter_initialize_converter(bsp_uboot_board_info.bi_intfreq); #endif /* HAS_UBOOT */ @@ -108,14 +109,15 @@ void bsp_start(void) ctx->clock = BSP_bus_frequency; #ifdef HAS_UBOOT - ctx->initial_baud = bsp_uboot_board_info.bi_baudrate; + #ifdef U_BOOT_GENERIC_BOARD_INFO + ctx->initial_baud = 115200; + #else + ctx->initial_baud = bsp_uboot_board_info.bi_baudrate; + #endif #endif } } - /* Disable decrementer */ - PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE); - /* Initialize exception handler */ ppc_exc_initialize_with_vector_base( (uintptr_t) bsp_section_work_begin, @@ -134,5 +136,9 @@ void bsp_start(void) bsp_interrupt_initialize(); /* Disable boot page translation */ +#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) + qoriq.lcc.bstar &= ~LCC_BSTAR_EN; +#else qoriq.lcc.bptr &= ~BPTR_EN; +#endif } diff --git a/c/src/lib/libbsp/powerpc/qoriq/startup/linkcmds.qoriq_t2080rdb b/c/src/lib/libbsp/powerpc/qoriq/startup/linkcmds.qoriq_t2080rdb new file mode 100644 index 0000000000..951a0ee684 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/qoriq/startup/linkcmds.qoriq_t2080rdb @@ -0,0 +1,36 @@ +/** + * @file + * + * Memory map for T2080RDB. + */ + +MEMORY { + LOW : ORIGIN = 0x4000, LENGTH = 16M - 16k + HIGH : ORIGIN = 0x1000000, LENGTH = 2048M - 16M + EMPTY : ORIGIN = 0x0, LENGTH = 0 +} + +REGION_ALIAS ("REGION_START", LOW); +REGION_ALIAS ("REGION_FAST_TEXT", LOW); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", LOW); +REGION_ALIAS ("REGION_TEXT", LOW); +REGION_ALIAS ("REGION_TEXT_LOAD", LOW); +REGION_ALIAS ("REGION_RODATA", HIGH); +REGION_ALIAS ("REGION_RODATA_LOAD", LOW); +REGION_ALIAS ("REGION_FAST_DATA", HIGH); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", LOW); +REGION_ALIAS ("REGION_DATA", HIGH); +REGION_ALIAS ("REGION_DATA_LOAD", LOW); +REGION_ALIAS ("REGION_BSS", HIGH); +REGION_ALIAS ("REGION_RWEXTRA", HIGH); +REGION_ALIAS ("REGION_WORK", HIGH); +REGION_ALIAS ("REGION_STACK", HIGH); +REGION_ALIAS ("REGION_NOCACHE", EMPTY); +REGION_ALIAS ("REGION_NOCACHE_LOAD", EMPTY); +REGION_ALIAS ("REGION_NVRAM", EMPTY); + +bsp_section_robarrier_align = 0x1000000; +bsp_section_rwbarrier_align = 0x1000000; +qoriq = 0xfe000000; + +INCLUDE linkcmds.base diff --git a/c/src/lib/libbsp/powerpc/qoriq/startup/linkcmds.qoriq_t4240rdb b/c/src/lib/libbsp/powerpc/qoriq/startup/linkcmds.qoriq_t4240rdb new file mode 100644 index 0000000000..b2f38b789c --- /dev/null +++ b/c/src/lib/libbsp/powerpc/qoriq/startup/linkcmds.qoriq_t4240rdb @@ -0,0 +1,7 @@ +/** + * @file + * + * Memory map for T4240RDB. + */ + +INCLUDE linkcmds.qoriq_t2080rdb diff --git a/c/src/lib/libbsp/powerpc/qoriq/startup/mmu-config.c b/c/src/lib/libbsp/powerpc/qoriq/startup/mmu-config.c index 2d81125d90..5b759fbbe1 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/startup/mmu-config.c +++ b/c/src/lib/libbsp/powerpc/qoriq/startup/mmu-config.c @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2011-2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -105,7 +105,7 @@ void TEXT qoriq_mmu_config(int first_tlb, int scratch_tlb) qoriq_mmu_context_init(&context); - for (i = 0; i < 16; ++i) { + for (i = 0; i < QORIQ_TLB1_ENTRY_COUNT; ++i) { if (i != scratch_tlb) { qoriq_tlb1_invalidate(i); } @@ -126,6 +126,6 @@ void TEXT qoriq_mmu_config(int first_tlb, int scratch_tlb) } } - qoriq_mmu_partition(&context, 8); + qoriq_mmu_partition(&context, (3 * QORIQ_TLB1_ENTRY_COUNT) / 4); qoriq_mmu_write_to_tlb1(&context, first_tlb); } diff --git a/c/src/lib/libbsp/powerpc/qoriq/startup/mmu.c b/c/src/lib/libbsp/powerpc/qoriq/startup/mmu.c index 0e52f0ab32..e2a0188c80 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/startup/mmu.c +++ b/c/src/lib/libbsp/powerpc/qoriq/startup/mmu.c @@ -7,10 +7,10 @@ */ /* - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH - * Obere Lagerstr. 30 + * Dornierstr. 4 * 82178 Puchheim * Germany * <rtems@embedded-brains.de> @@ -40,6 +40,21 @@ static uint32_t TEXT power_of_two(uint32_t val) return power; } +static uint32_t TEXT max_power_of_two(uint32_t val) +{ + uint32_t test_power = QORIQ_MMU_MIN_POWER; + uint32_t power = test_power; + uint32_t max = 1U << test_power; + + do { + power = test_power; + max <<= QORIQ_MMU_POWER_STEP; + test_power += QORIQ_MMU_POWER_STEP; + } while (test_power <= QORIQ_MMU_MAX_POWER && max <= val); + + return power; +} + void TEXT qoriq_mmu_context_init(qoriq_mmu_context *self) { int *cur = (int *) self; @@ -150,7 +165,7 @@ static void TEXT align(qoriq_mmu_context *self, uint32_t alignment) static bool TEXT is_full(qoriq_mmu_context *self) { - return self->count >= QORIQ_MMU_ENTRY_COUNT; + return self->count >= QORIQ_TLB1_ENTRY_COUNT; } static void TEXT append(qoriq_mmu_context *self, const qoriq_mmu_entry *new_entry) @@ -208,9 +223,8 @@ static bool TEXT split(qoriq_mmu_context *self, qoriq_mmu_entry *cur) uint32_t end = cur->last + 1; uint32_t size = end - begin; uint32_t begin_power = power_of_two(begin); - uint32_t end_power = power_of_two(end); - uint32_t size_power = power_of_two(size); - uint32_t power = min(begin_power, min(end_power, size_power)); + uint32_t size_power = max_power_of_two(size); + uint32_t power = min(begin_power, size_power); uint32_t split_size = power < 32 ? (1U << power) : 0; uint32_t split_pos = begin + split_size; diff --git a/c/src/lib/libbsp/shared/include/fatal.h b/c/src/lib/libbsp/shared/include/fatal.h index ba6cd51fa7..45db9d43bd 100644 --- a/c/src/lib/libbsp/shared/include/fatal.h +++ b/c/src/lib/libbsp/shared/include/fatal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2012-2015 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -111,7 +111,10 @@ typedef enum { /* ARM fatal codes */ ARM_FATAL_L2C_310_UNEXPECTED_ID = BSP_FATAL_CODE_BLOCK(9), ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS, - ARM_FATAL_L2C_310_EXCLUSIVE_CONFIG + ARM_FATAL_L2C_310_EXCLUSIVE_CONFIG, + + /* QorIQ fatal codes */ + QORIQ_FATAL_SMP_IPI_HANDLER_INSTALL = BSP_FATAL_CODE_BLOCK(10) } bsp_fatal_code; RTEMS_COMPILER_NO_RETURN_ATTRIBUTE static inline void |