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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-28 13:55:29 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-29 10:04:37 +0200 |
| commit | dffc08c0e9e0fdaa2911edf8b5067298ba468ed8 (patch) | |
| tree | 6f8b668222b9b24adfe0205b0d5c8b68594e77de | |
| parent | riscv: Implement _CPU_Context_validate() (diff) | |
| download | rtems-dffc08c0e9e0fdaa2911edf8b5067298ba468ed8.tar.bz2 | |
riscv: Fix interrupt save/restore
Update #3433.
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-exception-handler.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index 0bdfa2f481..cc47bbb7c1 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -80,7 +80,7 @@ SYM(ISR_Handler): SREG x26, (26 * CPU_SIZEOF_POINTER)(sp) SREG x27, (27 * CPU_SIZEOF_POINTER)(sp) SREG x28, (28 * CPU_SIZEOF_POINTER)(sp) - SREG x29, (28 * CPU_SIZEOF_POINTER)(sp) + SREG x29, (29 * CPU_SIZEOF_POINTER)(sp) SREG x30, (30 * CPU_SIZEOF_POINTER)(sp) SREG x31, (31 * CPU_SIZEOF_POINTER)(sp) |