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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-03-25 11:40:08 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-03-25 13:17:54 +0100 |
| commit | cb4dd48e06e115d7ccf7639bbbeaae300809857d (patch) | |
| tree | cfc0eb3a3d60e841ab3f6f216378b7a8f45c9f22 | |
| parent | testsupport: Generate unique worker names (diff) | |
| download | rtems-cb4dd48e06e115d7ccf7639bbbeaae300809857d.tar.bz2 | |
sparc: Ensure interrupt service after ISR enable
| -rw-r--r-- | cpukit/score/cpu/sparc/rtems/score/sparc.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/cpukit/score/cpu/sparc/rtems/score/sparc.h b/cpukit/score/cpu/sparc/rtems/score/sparc.h index ac8c510e46..45df6ff035 100644 --- a/cpukit/score/cpu/sparc/rtems/score/sparc.h +++ b/cpukit/score/cpu/sparc/rtems/score/sparc.h @@ -320,7 +320,14 @@ static inline uint32_t sparc_disable_interrupts(void) static inline void sparc_enable_interrupts(uint32_t psr) { register uint32_t _psr __asm__("g1") = psr; /* input to trap handler */ - __asm__ volatile ( "ta %0\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr)); + + /* + * The trap instruction has a higher trap priority than the interrupts + * according to "The SPARC Architecture Manual: Version 8", Table 7-1 + * "Exception and Interrupt Request Priority and tt Values". Add a nop to + * prevent a trap instruction right after the interrupt enable trap. + */ + __asm__ volatile ( "ta %0\nnop\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr)); } /** |