bsps/arm: Add PL111 support

7 files changed, 561 insertions, 1 deletions

diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am b/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am
index 9410a30a4a..7b961b36d3 100644
--- a/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am
+++ b/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am
@@ -43,6 +43,8 @@ include_bsp_HEADERS += ../shared/include/arm-gic-regs.h
 include_bsp_HEADERS += ../shared/include/arm-gic-tm27.h
 include_bsp_HEADERS += ../shared/include/arm-pl011.h
 include_bsp_HEADERS += ../shared/include/arm-pl011-regs.h
+include_bsp_HEADERS += ../shared/include/arm-pl111-fb.h
+include_bsp_HEADERS += ../shared/include/arm-pl111-regs.h
 include_bsp_HEADERS += include/irq.h
 
 include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h
@@ -124,6 +126,10 @@ libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
 # Start hooks
 libbsp_a_SOURCES += startup/bspstarthooks.c
 
+# Framebuffer
+libbsp_a_SOURCES += ../shared/arm-pl111-fb.c
+libbsp_a_SOURCES += startup/fb-config.c
+
 if HAS_SMP
 libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c
 endif
diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/include/bsp.h b/c/src/lib/libbsp/arm/realview-pbx-a9/include/bsp.h
index c25c9f62dc..05c0fd088d 100644
--- a/c/src/lib/libbsp/arm/realview-pbx-a9/include/bsp.h
+++ b/c/src/lib/libbsp/arm/realview-pbx-a9/include/bsp.h
@@ -19,6 +19,8 @@
 
 #define BSP_FEATURE_IRQ_EXTENSION
 
+#define BSP_HAS_FRAME_BUFFER 1
+
 #ifndef ASM
 
 #include <rtems.h>
@@ -41,7 +43,10 @@ extern "C" {
 
 typedef enum {
   BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL,
-  BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE
+  BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE,
+  BSP_ARM_PL111_FATAL_REGISTER_DEV,
+  BSP_ARM_PL111_FATAL_SEM_CREATE,
+  BSP_ARM_PL111_FATAL_SEM_RELEASE
 } rvpbxa9_fatal_code;
 
 void rvpbxa9_fatal(rvpbxa9_fatal_code code) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am b/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am
index 56e4ac8ac1..fad0cf93f2 100644
--- a/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am
+++ b/c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am
@@ -126,6 +126,14 @@ $(PROJECT_INCLUDE)/bsp/arm-pl011-regs.h: ../shared/include/arm-pl011-regs.h $(PR
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-pl011-regs.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-pl011-regs.h
 
+$(PROJECT_INCLUDE)/bsp/arm-pl111-fb.h: ../shared/include/arm-pl111-fb.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-pl111-fb.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-pl111-fb.h
+
+$(PROJECT_INCLUDE)/bsp/arm-pl111-regs.h: ../shared/include/arm-pl111-regs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-pl111-regs.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-pl111-regs.h
+
 $(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/startup/fb-config.c b/c/src/lib/libbsp/arm/realview-pbx-a9/startup/fb-config.c
new file mode 100644
index 0000000000..c2c4aaae00
--- /dev/null
+++ b/c/src/lib/libbsp/arm/realview-pbx-a9/startup/fb-config.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp/arm-pl111-fb.h>
+#include <bsp.h>
+
+static const pl111_fb_config fb_config = {
+  .regs = (volatile pl111 *) 0x10020000,
+
+  /*
+   * Values obtained from "RealView Platform Baseboard Explore for Cortex-A9
+   * User Guide" section 4.6.1 "Display resolutions and display memory
+   * organization".
+   */
+  .timing0 = 0x3f1f3f9c,
+  .timing1 = 0x090b61df,
+  .timing2 = 0x067f1800,
+
+  .timing3 = 0x0,
+  .control = PL111_LCD_CONTROL_LCD_TFT
+    | PL111_LCD_CONTROL_LCD_BPP(PL111_LCD_CONTROL_LCD_BPP_16),
+  .power_delay_in_us = 100000
+};
+
+const pl111_fb_config *arm_pl111_fb_get_config(void)
+{
+  return &fb_config;
+}
+
+void arm_pl111_fb_pins_set_up(const pl111_fb_config *cfg)
+{
+  /* TODO */
+}
+
+void arm_pl111_fb_pins_tear_down(const pl111_fb_config *cfg)
+{
+  /* TODO */
+}
diff --git a/c/src/lib/libbsp/arm/shared/arm-pl111-fb.c b/c/src/lib/libbsp/arm/shared/arm-pl111-fb.c
new file mode 100644
index 0000000000..2947eda7d1
--- /dev/null
+++ b/c/src/lib/libbsp/arm/shared/arm-pl111-fb.c
@@ -0,0 +1,280 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <errno.h>
+#include <assert.h>
+#include <stdlib.h>
+
+#include <rtems/framebuffer.h>
+#include <rtems/fb.h>
+#include <rtems/libio.h>
+
+#include <bsp.h>
+#include <bsp/arm-pl111-fb.h>
+
+typedef struct {
+  rtems_id semaphore;
+  void *frame_buffer;
+} pl111_fb_context;
+
+static pl111_fb_context pl111_fb_instance;
+
+static const uint8_t pl111_bits_per_pixel[] = { 1, 2, 4, 8, 16, 24, 16, 12 };
+
+static uint32_t pl111_fb_get_width(const pl111_fb_config *cfg)
+{
+  return 16U * (PL111_LCD_TIMING0_PPL_GET(cfg->timing0) + 1U);
+}
+
+static uint32_t pl111_fb_get_height(const pl111_fb_config *cfg)
+{
+  return PL111_LCD_TIMING1_LPP_GET(cfg->timing1) + 1U;
+}
+
+static uint32_t pl111_fb_get_bits_per_pixel(const pl111_fb_config *cfg)
+{
+  return pl111_bits_per_pixel[PL111_LCD_CONTROL_LCD_BPP_GET(cfg->control)];
+}
+
+static uint32_t pl111_fb_get_line_length_in_bytes(const pl111_fb_config *cfg)
+{
+  uint32_t width = pl111_fb_get_width(cfg);
+  uint32_t bits_per_pixel = pl111_fb_get_bits_per_pixel(cfg);
+
+  return width * ((bits_per_pixel + 7U) / 8U);
+}
+
+static uint32_t pl111_fb_get_frame_buffer_size(const pl111_fb_config *cfg)
+{
+  uint32_t line_length_in_bytes = pl111_fb_get_line_length_in_bytes(cfg);
+  uint32_t height = pl111_fb_get_height(cfg);
+
+  return height * line_length_in_bytes;
+}
+
+static void pl111_fb_power_delay(const pl111_fb_config *cfg)
+{
+  rtems_interval delay = (cfg->power_delay_in_us + 1)
+    / rtems_configuration_get_microseconds_per_tick();
+  rtems_status_code sc = rtems_task_wake_after(delay);
+  assert(sc == RTEMS_SUCCESSFUL);
+}
+
+static rtems_status_code pl111_fb_initialize(pl111_fb_context *ctx)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+  const pl111_fb_config *cfg = arm_pl111_fb_get_config();
+
+  ctx->frame_buffer = calloc(1, pl111_fb_get_frame_buffer_size(cfg));
+  if (ctx->frame_buffer != NULL) {
+    volatile pl111 *regs = cfg->regs;
+
+    regs->lcd.upbase = (uint32_t) ctx->frame_buffer;
+
+    regs->lcd.timing0 = cfg->timing0;
+    regs->lcd.timing1 = cfg->timing1;
+    regs->lcd.timing2 = cfg->timing2;
+    regs->lcd.timing3 = cfg->timing3;
+    regs->lcd.control = cfg->control;
+
+    arm_pl111_fb_pins_set_up(cfg);
+
+    regs->lcd.control = cfg->control
+      | PL111_LCD_CONTROL_LCD_EN;
+
+    pl111_fb_power_delay(cfg);
+
+    regs->lcd.control = cfg->control
+      | PL111_LCD_CONTROL_LCD_EN
+      | PL111_LCD_CONTROL_LCD_PWR;
+  } else {
+    sc = RTEMS_NO_MEMORY;
+  }
+
+  return sc;
+}
+
+static void pl111_fb_destroy(const pl111_fb_context *ctx)
+{
+  const pl111_fb_config *cfg = arm_pl111_fb_get_config();
+  volatile pl111 *regs = cfg->regs;
+
+  free(ctx->frame_buffer);
+
+  regs->lcd.control = cfg->control
+    | PL111_LCD_CONTROL_LCD_EN;
+
+  pl111_fb_power_delay(cfg);
+
+  regs->lcd.control = cfg->control;
+
+  arm_pl111_fb_pins_tear_down(cfg);
+}
+
+static void pl111_fb_get_fix_screen_info(struct fb_fix_screeninfo *info)
+{
+  const pl111_fb_config *cfg = arm_pl111_fb_get_config();
+  const pl111_fb_context *ctx = &pl111_fb_instance;
+
+  memset(info, 0, sizeof(*info));
+
+  info->smem_start = ctx->frame_buffer;
+  info->smem_len = pl111_fb_get_frame_buffer_size(cfg);
+  info->type = FB_TYPE_PACKED_PIXELS;
+  info->visual = FB_VISUAL_TRUECOLOR;
+  info->line_length = pl111_fb_get_line_length_in_bytes(cfg);
+}
+
+static void pl111_fb_get_var_screen_info(struct fb_var_screeninfo *info)
+{
+  const pl111_fb_config *cfg = arm_pl111_fb_get_config();
+
+  memset(info, 0, sizeof(*info));
+
+  info->xres = pl111_fb_get_width(cfg);
+  info->yres = pl111_fb_get_height(cfg);
+  info->bits_per_pixel = pl111_fb_get_bits_per_pixel(cfg);
+}
+
+static void pl111_fb_release(const pl111_fb_context *ctx)
+{
+  rtems_status_code sc = rtems_semaphore_release(ctx->semaphore);
+  if (sc != RTEMS_SUCCESSFUL) {
+    rtems_fatal(
+      RTEMS_FATAL_SOURCE_BSP_SPECIFIC,
+      BSP_ARM_PL111_FATAL_SEM_RELEASE
+    );
+  }
+}
+
+rtems_device_driver frame_buffer_initialize(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *arg
+)
+{
+  rtems_status_code sc;
+  pl111_fb_context *ctx = &pl111_fb_instance;
+
+  sc = rtems_io_register_name(FRAMEBUFFER_DEVICE_0_NAME, major, 0);
+  if (sc != RTEMS_SUCCESSFUL) {
+    rtems_fatal(
+      RTEMS_FATAL_SOURCE_BSP_SPECIFIC,
+      BSP_ARM_PL111_FATAL_REGISTER_DEV
+    );
+  }
+
+  sc = rtems_semaphore_create(
+    rtems_build_name('F', 'B', ' ', ' '),
+    1,
+    RTEMS_COUNTING_SEMAPHORE,
+    0,
+    &ctx->semaphore
+  );
+  if (sc != RTEMS_SUCCESSFUL) {
+    rtems_fatal(
+      RTEMS_FATAL_SOURCE_BSP_SPECIFIC,
+      BSP_ARM_PL111_FATAL_SEM_CREATE
+    );
+  }
+
+  return sc;
+}
+
+rtems_device_driver frame_buffer_open(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *arg
+)
+{
+  rtems_status_code sc;
+  pl111_fb_context *ctx = &pl111_fb_instance;
+
+  sc = rtems_semaphore_obtain(
+    ctx->semaphore,
+    RTEMS_WAIT,
+    RTEMS_NO_TIMEOUT
+  );
+  if (sc == RTEMS_SUCCESSFUL) {
+    sc = pl111_fb_initialize(ctx);
+    if (sc != RTEMS_SUCCESSFUL) {
+      pl111_fb_release(ctx);
+    }
+  }
+
+  return sc;
+}
+
+rtems_device_driver frame_buffer_close(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *arg
+)
+{
+  const pl111_fb_context *ctx = &pl111_fb_instance;
+
+  pl111_fb_destroy(ctx);
+  pl111_fb_release(ctx);
+
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_device_driver frame_buffer_read(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *arg
+)
+{
+  return RTEMS_IO_ERROR;
+}
+
+rtems_device_driver frame_buffer_write(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *arg
+)
+{
+  return RTEMS_IO_ERROR;
+}
+
+rtems_device_driver frame_buffer_control(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *arg
+)
+{
+  rtems_libio_ioctl_args_t *ioctl_arg = arg;
+  int eno = 0;
+
+  switch (ioctl_arg->command) {
+    case FBIOGET_FSCREENINFO:
+      pl111_fb_get_fix_screen_info(ioctl_arg->buffer);
+      break;
+    case FBIOGET_VSCREENINFO:
+      pl111_fb_get_var_screen_info(ioctl_arg->buffer);
+      break;
+    default:
+      eno = EINVAL;
+      break;
+  }
+
+  if (eno == 0) {
+    ioctl_arg->ioctl_return = 0;
+  } else {
+    ioctl_arg->ioctl_return = -1;
+    errno = eno;
+  }
+
+  return RTEMS_SUCCESSFUL;
+}
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-pl111-fb.h b/c/src/lib/libbsp/arm/shared/include/arm-pl111-fb.h
new file mode 100644
index 0000000000..0503c6c172
--- /dev/null
+++ b/c/src/lib/libbsp/arm/shared/include/arm-pl111-fb.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_PL111_FB_H
+#define LIBBSP_ARM_SHARED_ARM_PL111_FB_H
+
+#include <bsp/arm-pl111-regs.h>
+
+typedef struct {
+  volatile pl111 *regs;
+  uint32_t timing0;
+  uint32_t timing1;
+  uint32_t timing2;
+  uint32_t timing3;
+  uint32_t control;
+  uint32_t power_delay_in_us;
+} pl111_fb_config;
+
+const pl111_fb_config *arm_pl111_fb_get_config(void);
+
+void arm_pl111_fb_pins_set_up(const pl111_fb_config *cfg);
+
+void arm_pl111_fb_pins_tear_down(const pl111_fb_config *cfg);
+
+#endif /* LIBBSP_ARM_SHARED_ARM_PL111_FB_H */
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-pl111-regs.h b/c/src/lib/libbsp/arm/shared/include/arm-pl111-regs.h
new file mode 100644
index 0000000000..02ea3f43e3
--- /dev/null
+++ b/c/src/lib/libbsp/arm/shared/include/arm-pl111-regs.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
+#define LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+	uint32_t timing0;
+#define PL111_LCD_TIMING0_PPL(val) BSP_FLD32(val, 2, 7)
+#define PL111_LCD_TIMING0_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
+#define PL111_LCD_TIMING0_PPL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 7)
+#define PL111_LCD_TIMING0_HSW(val) BSP_FLD32(val, 8, 15)
+#define PL111_LCD_TIMING0_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define PL111_LCD_TIMING0_HSW_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define PL111_LCD_TIMING0_HFP(val) BSP_FLD32(val, 16, 23)
+#define PL111_LCD_TIMING0_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define PL111_LCD_TIMING0_HFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define PL111_LCD_TIMING0_HBP(val) BSP_FLD32(val, 24, 31)
+#define PL111_LCD_TIMING0_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define PL111_LCD_TIMING0_HBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+	uint32_t timing1;
+#define PL111_LCD_TIMING1_LPP(val) BSP_FLD32(val, 0, 9)
+#define PL111_LCD_TIMING1_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
+#define PL111_LCD_TIMING1_LPP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
+#define PL111_LCD_TIMING1_VSW(val) BSP_FLD32(val, 10, 15)
+#define PL111_LCD_TIMING1_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
+#define PL111_LCD_TIMING1_VSW_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15)
+#define PL111_LCD_TIMING1_VFP(val) BSP_FLD32(val, 16, 23)
+#define PL111_LCD_TIMING1_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define PL111_LCD_TIMING1_VFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define PL111_LCD_TIMING1_VBP(val) BSP_FLD32(val, 24, 31)
+#define PL111_LCD_TIMING1_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define PL111_LCD_TIMING1_VBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+	uint32_t timing2;
+#define PL111_LCD_TIMING2_PCD_LO(val) BSP_FLD32(val, 0, 4)
+#define PL111_LCD_TIMING2_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define PL111_LCD_TIMING2_PCD_LO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+#define PL111_LCD_TIMING2_CLKSEL BSP_BIT32(5)
+#define PL111_LCD_TIMING2_ACB(val) BSP_FLD32(val, 6, 10)
+#define PL111_LCD_TIMING2_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
+#define PL111_LCD_TIMING2_ACB_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10)
+#define PL111_LCD_TIMING2_IVS BSP_BIT32(11)
+#define PL111_LCD_TIMING2_IHS BSP_BIT32(12)
+#define PL111_LCD_TIMING2_IPC BSP_BIT32(13)
+#define PL111_LCD_TIMING2_IOE BSP_BIT32(14)
+#define PL111_LCD_TIMING2_CPL(val) BSP_FLD32(val, 16, 25)
+#define PL111_LCD_TIMING2_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
+#define PL111_LCD_TIMING2_CPL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
+#define PL111_LCD_TIMING2_BCD BSP_BIT32(26)
+#define PL111_LCD_TIMING2_PCD_HI(val) BSP_FLD32(val, 27, 31)
+#define PL111_LCD_TIMING2_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
+#define PL111_LCD_TIMING2_PCD_HI_SET(reg, val) BSP_FLD32SET(reg, val, 27, 31)
+	uint32_t timing3;
+#define PL111_LCD_TIMING3_LED(val) BSP_FLD32(val, 0, 6)
+#define PL111_LCD_TIMING3_LED_GET(reg) BSP_FLD32GET(reg, 0, 6)
+#define PL111_LCD_TIMING3_LED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6)
+#define PL111_LCD_TIMING3_LEE BSP_BIT32(16)
+	uint32_t upbase;
+	uint32_t lpbase;
+	uint32_t control;
+#define PL111_LCD_CONTROL_LCD_EN BSP_BIT32(0)
+#define PL111_LCD_CONTROL_LCD_BPP(val) BSP_FLD32(val, 1, 3)
+#define PL111_LCD_CONTROL_LCD_BPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
+#define PL111_LCD_CONTROL_LCD_BPP_SET(reg, val) BSP_FLD32SET(reg, val, 1, 3)
+#define PL111_LCD_CONTROL_LCD_BPP_1 0x00U
+#define PL111_LCD_CONTROL_LCD_BPP_2 0x01U
+#define PL111_LCD_CONTROL_LCD_BPP_4 0x02U
+#define PL111_LCD_CONTROL_LCD_BPP_8 0x03U
+#define PL111_LCD_CONTROL_LCD_BPP_16 0x04U
+#define PL111_LCD_CONTROL_LCD_BPP_24 0x05U
+#define PL111_LCD_CONTROL_LCD_BPP_16 0x06U
+#define PL111_LCD_CONTROL_LCD_BPP_12 0x07U
+#define PL111_LCD_CONTROL_LCD_BW BSP_BIT32(4)
+#define PL111_LCD_CONTROL_LCD_TFT BSP_BIT32(5)
+#define PL111_LCD_CONTROL_LCD_MONO8 BSP_BIT32(6)
+#define PL111_LCD_CONTROL_LCD_DUAL BSP_BIT32(7)
+#define PL111_LCD_CONTROL_BGR BSP_BIT32(8)
+#define PL111_LCD_CONTROL_BEBO BSP_BIT32(9)
+#define PL111_LCD_CONTROL_BEPO BSP_BIT32(10)
+#define PL111_LCD_CONTROL_LCD_PWR BSP_BIT32(11)
+#define PL111_LCD_CONTROL_LCD_V_COMP(val) BSP_FLD32(val, 12, 13)
+#define PL111_LCD_CONTROL_LCD_V_COMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
+#define PL111_LCD_CONTROL_LCD_V_COMP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
+#define PL111_LCD_CONTROL_WATERMARK BSP_BIT32(16)
+	uint32_t imsc;
+	uint32_t ris;
+	uint32_t mis;
+	uint32_t icr;
+#define PL111_LCD_I_FUF BSP_BIT32(1)
+#define PL111_LCD_I_LNBU BSP_BIT32(2)
+#define PL111_LCD_I_VCOMP BSP_BIT32(3)
+#define PL111_LCD_I_MBERROR BSP_BIT32(4)
+	uint32_t upcurr;
+	uint32_t lpcurr;
+	uint32_t reserved_34[115];
+	uint16_t pal[256];
+#define PL111_LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
+#define PL111_LCD_PAL_R_GET(reg) BSP_FLD16GET(reg, 0, 4)
+#define PL111_LCD_PAL_R_SET(reg, val) BSP_FLD16SET(reg, val, 0, 4)
+#define PL111_LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
+#define PL111_LCD_PAL_G_GET(reg) BSP_FLD16GET(reg, 5, 9)
+#define PL111_LCD_PAL_G_SET(reg, val) BSP_FLD16SET(reg, val, 5, 9)
+#define PL111_LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
+#define PL111_LCD_PAL_B_GET(reg) BSP_FLD16GET(reg, 10, 14)
+#define PL111_LCD_PAL_B_SET(reg, val) BSP_FLD16SET(reg, val, 10, 14)
+#define PL111_LCD_PAL_I BSP_BIT16(15)
+} pl111_lcd;
+
+typedef struct {
+	uint8_t image[1024];
+	uint32_t ctrl;
+#define PL111_CRSR_CTRL_ON BSP_BIT32(0)
+#define PL111_CRSR_CTRL_NUMBER(val) BSP_FLD32(val, 4, 5)
+#define PL111_CRSR_CTRL_NUMBER_GET(reg) BSP_FLD32GET(reg, 4, 5)
+#define PL111_CRSR_CTRL_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
+	uint32_t config;
+#define PL111_CRSR_CONFIG_SIZE BSP_BIT32(0)
+#define PL111_CRSR_CONFIG_FRAME_SYNC BSP_BIT32(1)
+	uint32_t palette0;
+	uint32_t palette1;
+#define PL111_CRSR_PALETTE_RED(val) BSP_FLD32(val, 0, 7)
+#define PL111_CRSR_PALETTE_RED_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define PL111_CRSR_PALETTE_RED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+#define PL111_CRSR_PALETTE_GREEN(val) BSP_FLD32(val, 8, 15)
+#define PL111_CRSR_PALETTE_GREEN_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define PL111_CRSR_PALETTE_GREEN_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define PL111_CRSR_PALETTE_BLUE(val) BSP_FLD32(val, 16, 23)
+#define PL111_CRSR_PALETTE_BLUE_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define PL111_CRSR_PALETTE_BLUE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+	uint32_t xy;
+#define PL111_CRSR_XY_X(val) BSP_FLD32(val, 0, 9)
+#define PL111_CRSR_XY_X_GET(reg) BSP_FLD32GET(reg, 0, 9)
+#define PL111_CRSR_XY_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
+#define PL111_CRSR_XY_X_EXP(val) BSP_FLD32(val, 10, 11)
+#define PL111_CRSR_XY_X_EXP_GET(reg) BSP_FLD32GET(reg, 10, 11)
+#define PL111_CRSR_XY_X_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11)
+#define PL111_CRSR_XY_Y(val) BSP_FLD32(val, 16, 25)
+#define PL111_CRSR_XY_Y_GET(reg) BSP_FLD32GET(reg, 16, 25)
+#define PL111_CRSR_XY_Y_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
+#define PL111_CRSR_XY_Y_EXP(val) BSP_FLD32(val, 25, 27)
+#define PL111_CRSR_XY_Y_EXP_GET(reg) BSP_FLD32GET(reg, 25, 27)
+#define PL111_CRSR_XY_Y_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 25, 27)
+	uint32_t clip;
+#define PL111_CRSR_CLIP_X(val) BSP_FLD32(val, 0, 5)
+#define PL111_CRSR_CLIP_X_GET(reg) BSP_FLD32GET(reg, 0, 5)
+#define PL111_CRSR_CLIP_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
+#define PL111_CRSR_CLIP_Y(val) BSP_FLD32(val, 8, 13)
+#define PL111_CRSR_CLIP_Y_GET(reg) BSP_FLD32GET(reg, 8, 13)
+#define PL111_CRSR_CLIP_Y_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
+	uint32_t imsc;
+	uint32_t icr;
+	uint32_t ris;
+	uint32_t mis;
+#define PL111_CRSR_I_CRSR BSP_BIT32(0)
+} pl111_crsr;
+
+typedef struct {
+	pl111_lcd lcd;
+	uint32_t reserved_400[256];
+	pl111_crsr crsr;
+} pl111;
+
+#endif /* LIBBSP_ARM_SHARED_ARM_PL111_REGS_H */