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authorSebastian Huber <sebastian.huber@embedded-brains.de>2014-02-26 12:14:27 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2014-02-28 09:06:19 +0100
commitc5b1e208c5694175deabcefdc02516011c4287a8 (patch)
tree0dd1534510f04095f37997d8e04e74952f3e223b
parentbsp/leon3: Add new cache manager implementation (diff)
downloadrtems-c5b1e208c5694175deabcefdc02516011c4287a8.tar.bz2
bsp/leon3: Add L2C registers
-rw-r--r--c/src/lib/libbsp/sparc/shared/include/grlib.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/sparc/shared/include/grlib.h b/c/src/lib/libbsp/sparc/shared/include/grlib.h
index 9c45038d3a..5a1449f3e5 100644
--- a/c/src/lib/libbsp/sparc/shared/include/grlib.h
+++ b/c/src/lib/libbsp/sparc/shared/include/grlib.h
@@ -88,6 +88,31 @@ struct grgpio_regs {
volatile unsigned int bypass; /* 0x18 Bypass register */
};
+/* L2C - Level 2 Cache Controller registers */
+struct l2c_regs {
+ volatile unsigned int control;
+ volatile unsigned int status;
+ volatile unsigned int flush_mem_addr;
+ volatile unsigned int flush_set_index;
+ volatile unsigned int access_counter;
+ volatile unsigned int hit_counter;
+ volatile unsigned int bus_cycle_counter;
+ volatile unsigned int bus_usage_counter;
+ volatile unsigned int error_status_control;
+ volatile unsigned int error_addr;
+ volatile unsigned int tag_check_bit;
+ volatile unsigned int data_check_bit;
+ volatile unsigned int scrub_control_status;
+ volatile unsigned int scrub_delay;
+ volatile unsigned int error_injection;
+ volatile unsigned int reserved_3c[17];
+ volatile unsigned int mtrr;
+ volatile unsigned int reserved_84[131039];
+ volatile unsigned int diag_iface_tag[16384];
+ volatile unsigned int reserved_90000[376832];
+ volatile unsigned int diag_iface_data[524288];
+};
+
#ifdef __cplusplus
}
#endif