Merge branch 'master' of ssh://dispatch.rtems.org/data/git/rtems

6 files changed, 32 insertions, 13 deletions

diff --git a/cpukit/libblock/src/ramdisk-init.c b/cpukit/libblock/src/ramdisk-init.c
index 45b1329e6d..cc2ad3e0bb 100644
--- a/cpukit/libblock/src/ramdisk-init.c
+++ b/cpukit/libblock/src/ramdisk-init.c
@@ -36,7 +36,7 @@ ramdisk *ramdisk_allocate(
   bool trace
 )
 {
-  struct ramdisk *rd = malloc(sizeof(struct ramdisk));
+  struct ramdisk *rd = calloc(1, sizeof(*rd));
 
   if (rd == NULL) {
     return NULL;
diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
index d76dfa88b4..2718f80838 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
@@ -5,10 +5,10 @@
  */
 
 /*
- * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
+ * Copyright (c) 2011, 2016 Sebastian Huber.  All rights reserved.
  *
  *  embedded brains GmbH
- *  Obere Lagerstr. 30
+ *  Dornierstr. 4
  *  82178 Puchheim
  *  Germany
  *  <rtems@embedded-brains.de>
@@ -23,6 +23,7 @@
 #endif
 
 #include <rtems/score/armv7m.h>
+#include <rtems/rtems/cache.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
@@ -33,6 +34,14 @@ void _ARMV7M_Set_exception_handler(
 {
   if ( _ARMV7M_SCB->vtor [index] != handler ) {
     _ARMV7M_SCB->vtor [index] = handler;
+    rtems_cache_flush_multiple_data_lines(
+      &_ARMV7M_SCB->vtor [index],
+      sizeof(_ARMV7M_SCB->vtor [index])
+    );
+    rtems_cache_invalidate_multiple_instruction_lines(
+      &_ARMV7M_SCB->vtor [index],
+      sizeof(_ARMV7M_SCB->vtor [index])
+    );
   }
 }
 
diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h
index 6d1f8502a3..2114f773d4 100644
--- a/cpukit/score/cpu/arm/rtems/score/arm.h
+++ b/cpukit/score/cpu/arm/rtems/score/arm.h
@@ -29,7 +29,7 @@ extern "C" {
  */
 /**@{**/
 
-#if defined(__ARM_ARCH_7M__)
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
   #define CPU_MODEL_NAME "ARMv7M"
   #define ARM_MULTILIB_ARCH_V7M
 #elif defined(__ARM_ARCH_6M__)
diff --git a/doc/cpu_supplement/arm.t b/doc/cpu_supplement/arm.t
index e24ca00ca8..34fb017d22 100644
--- a/doc/cpu_supplement/arm.t
+++ b/doc/cpu_supplement/arm.t
@@ -73,6 +73,9 @@ with hard-float ABI VFP-D16 support
 integer division (SDIV/UDIV)
 @item @code{thumb/armv7-m/fpv4-sp-d16}: ARMv7-M, Thumb-2 instruction set with
 hardware integer division (SDIV/UDIV) and hard-float ABI FPv4-SP support
+@item @code{thumb/cortex-m7/fpv5-d16}: ARMv7M, Thumb-2 instruction set
+optimized for Cortex-M7 with hard-float ABI VFP-D16 support and support for the
+64-bit floating point unit
 @item @code{eb/thumb/armv7-r}: ARMv7-R, Big-endian Thumb-2 instruction set
 @item @code{eb/thumb/armv7-r/vfpv3-d16/hard}: ARMv7-R, Big-endian Thumb-2
 instruction set with hard-float ABI VFP-D16 support
@@ -82,15 +85,17 @@ Multilib 1. and 2. support the standard ARM7TDMI and ARM926EJ-S targets.
 
 Multilib 3. supports the Cortex-M0 and Cortex-M1 cores.
 
-Multilib 8. supports the Cortex-M3 and Cortex-M4 cores, which have a special
-hardware integer division instruction (this is not present in the A and R
-profiles).
+Multilib 8. supports the Cortex-M3, Cortex-M4 and Cortex-M7 cores, which have a
+special hardware integer division instruction (this is not present in the A and
+R profiles).
 
 Multilib 9. supports the Cortex-M4 cores with a floating point unit.
 
+Multilib 10. supports the Cortex-M7 core with a floating point unit.
+
 Multilib 4. and 5. support the Cortex-A processors.
 
-Multilib 6., 7., 10. and 11. support the Cortex-R processors.  Here also
+Multilib 6., 7., 11. and 12. support the Cortex-R processors.  Here also
 big-endian variants are available.
 
 Use for example the following GCC options
diff --git a/testsuites/sptests/sp37/init.c b/testsuites/sptests/sp37/init.c
index 2fbe1172c1..2059030f09 100644
--- a/testsuites/sptests/sp37/init.c
+++ b/testsuites/sptests/sp37/init.c
@@ -467,6 +467,10 @@ static void test_interrupt_body(void)
    */
   puts( "interrupt is in progress (use body)" );
   in_isr = rtems_interrupt_is_in_progress();
+
+  puts( "interrupt enable (use body)" );
+  rtems_interrupt_enable( level );
+
   if ( in_isr ) {
     puts( "interrupt reported to be is in progress (body)" );
     rtems_test_exit( 0 );
diff --git a/testsuites/sptests/sp37/sp37.scn b/testsuites/sptests/sp37/sp37.scn
index adfa9eedd4..e3349fce0d 100644
--- a/testsuites/sptests/sp37/sp37.scn
+++ b/testsuites/sptests/sp37/sp37.scn
@@ -1,4 +1,4 @@
-*** TEST 37 ***
+*** BEGIN OF TEST SP 37 ***
 clock_tick from task level
 Blocking task... suspending self
 clock_tick from task level with preempt -- OK
@@ -6,15 +6,16 @@ interrupt is in progress (use body)
 interrupt disable (use inline)
 interrupt flash (use inline)
 interrupt enable (use inline)
-interrupt level attribute (use inline)
+interrupt level mode (use inline)
 test case working..
-interrupt is in progress (use body)
 interrupt disable (use body)
 interrupt disable (use body)
 interrupt flash (use body)
 interrupt enable (use body)
-interrupt level attribute (use body)
+interrupt level mode (use body)
 test seems to work
+interrupt is in progress (use body)
+interrupt enable (use body)
 isr_in_progress(inline) from ISR -- OK
 isr_in_progress(body) from ISR -- OK
-*** END OF TEST 37 ***
+*** END OF TEST SP 37 ***