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authorSebastian Huber <sebastian.huber@embedded-brains.de>2017-07-31 13:34:46 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2017-07-31 13:43:38 +0200
commita597984b991a000bbd9aa9b3fe1b7c3365cc3c50 (patch)
treece1ce1fea6bc25539b8b029e1c4172f775a37386
parentbsps/powerpc: Fix format specifiers (diff)
downloadrtems-a597984b991a000bbd9aa9b3fe1b7c3365cc3c50.tar.bz2
powerpc: Add register defines
Update #3082. Update #3085.
-rw-r--r--cpukit/score/cpu/powerpc/rtems/powerpc/registers.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
index 46172099a4..6ce320e763 100644
--- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
+++ b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
@@ -355,6 +355,12 @@ lidate */
#define BOOKE_DAC2 317 /* Data Address Compare 2 */
#define BOOKE_DVC1 318 /* Data Value Compare 1 */
#define BOOKE_DVC2 319 /* Data Value Compare 2 */
+#define BOOKE_GSRR0 378 /* Guest Save/Restore Register 0 */
+#define BOOKE_GSRR1 379 /* Guest Save/Restore Register 1 */
+#define BOOKE_GEPR 380 /* Guest External Proxy Register */
+#define BOOKE_GDEAR 381 /* Guest Data Exception Address Register */
+#define BOOKE_GPIR 382 /* Guest Processor ID Register */
+#define BOOKE_GESR 383 /* Guest Exception Syndrome Register */
#define BOOKE_IVOR0 400 /* Interrupt Vector Offset Register 0 */
#define BOOKE_IVOR1 401 /* Interrupt Vector Offset Register 1 */
#define BOOKE_IVOR2 402 /* Interrupt Vector Offset Register 2 */
@@ -371,9 +377,29 @@ lidate */
#define BOOKE_IVOR13 413 /* Interrupt Vector Offset Register 13 */
#define BOOKE_IVOR14 414 /* Interrupt Vector Offset Register 14 */
#define BOOKE_IVOR15 415 /* Interrupt Vector Offset Register 15 */
+#define BOOKE_IVOR42 436 /* Interrupt Vector Offset Register 42 */
+#define BOOKE_IVOR32 528 /* Interrupt Vector Offset Register 32 */
+#define BOOKE_IVOR33 529 /* Interrupt Vector Offset Register 33 */
+#define BOOKE_IVOR34 530 /* Interrupt Vector Offset Register 34 */
+#define BOOKE_IVOR35 531 /* Interrupt Vector Offset Register 35 */
+#define BOOKE_IVOR36 532 /* Interrupt Vector Offset Register 36 */
+#define BOOKE_IVOR37 533 /* Interrupt Vector Offset Register 37 */
+#define BOOKE_IVOR38 432 /* Interrupt Vector Offset Register 38 */
+#define BOOKE_IVOR39 433 /* Interrupt Vector Offset Register 39 */
+#define BOOKE_IVOR40 434 /* Interrupt Vector Offset Register 40 */
+#define BOOKE_IVOR41 435 /* Interrupt Vector Offset Register 41 */
+#define BOOKE_GIVOR2 440 /* Guest Interrupt Vector Offset Register 2 */
+#define BOOKE_GIVOR3 441 /* Guest Interrupt Vector Offset Register 3 */
+#define BOOKE_GIVOR4 442 /* Guest Interrupt Vector Offset Register 4 */
+#define BOOKE_GIVOR8 443 /* Guest Interrupt Vector Offset Register 8 */
+#define BOOKE_GIVOR13 444 /* Guest Interrupt Vector Offset Register 13 */
+#define BOOKE_GIVOR14 445 /* Guest Interrupt Vector Offset Register 14 */
+#define BOOKE_GIVPR 446 /* Guest Interrupt Vector Prefix Register */
#define BOOKE_MCSRR0 570 /* Machine Check Save/Restore Register 0 */
#define BOOKE_MCSRR1 571 /* Machine Check Save/Restore Register 1 */
#define BOOKE_MCSR 572 /* Machine Check Status Register */
+#define BOOKE_DSRR0 574 /* Debug Save/Restore Register 0 */
+#define BOOKE_DSRR1 575 /* Debug Save/Restore Register 1 */
#define PPC440_INV0 880 /* Instruction Cache Normal Victim 0 */
#define PPC440_INV1 881 /* Instruction Cache Normal Victim 1 */