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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-27 08:08:10 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-29 10:04:36 +0200 |
| commit | 98f051efed0b415cce5c19d3f4a71858091a3cef (patch) | |
| tree | 4a090946c987046f1ed9ddd38cba89a78d5669dd | |
| parent | riscv: Enable interrupts during dispatch after ISR (diff) | |
| download | rtems-98f051efed0b415cce5c19d3f4a71858091a3cef.tar.bz2 | |
riscv: Remove RISCV_GCC_RED_ZONE_SIZE
The current ABI says that there is no stack red zone:
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
"Procedures must not rely upon the persistence of stack-allocated data
whose addresses lie below the stack pointer."
Update #3433.
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 3 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-initialize.c | 3 |
2 files changed, 1 insertions, 5 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 4d9f828086..564812c246 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -164,9 +164,6 @@ uint32_t _CPU_ISR_Get_level( void ); /* end of ISR handler macros */ -/* Context handler macros */ -#define RISCV_GCC_RED_ZONE_SIZE 128 - void _CPU_Context_Initialize( Context_Control *context, void *stack_area_begin, diff --git a/cpukit/score/cpu/riscv/riscv-context-initialize.c b/cpukit/score/cpu/riscv/riscv-context-initialize.c index 03fcc5c099..619c691f53 100644 --- a/cpukit/score/cpu/riscv/riscv-context-initialize.c +++ b/cpukit/score/cpu/riscv/riscv-context-initialize.c @@ -50,8 +50,7 @@ void _CPU_Context_Initialize( { uintptr_t stack = ((uintptr_t) stack_area_begin); - /* Account for red-zone */ - uintptr_t stack_high = stack + stack_area_size - RISCV_GCC_RED_ZONE_SIZE; + uintptr_t stack_high = stack + stack_area_size; memset(context, 0, sizeof(*context)); |