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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-31 09:15:00 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-08-01 10:08:59 +0200 |
| commit | 529154bad207a42a6d0f03343c7e215eab97ced5 (patch) | |
| tree | 36aa2259646b7b7305ede17450a7fca0b4ddd11b | |
| parent | bsp/riscv: Fix clock driver (diff) | |
| download | rtems-529154bad207a42a6d0f03343c7e215eab97ced5.tar.bz2 | |
bsp/riscv: Initialize FPU depending on ISA
Initialize fcsr to zero for a defined rounding mode.
Update #3433.
| -rw-r--r-- | bsps/riscv/riscv/start/start.S | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S index 290c95a166..feb07feedf 100644 --- a/bsps/riscv/riscv/start/start.S +++ b/bsps/riscv/riscv/start/start.S @@ -48,9 +48,12 @@ SYM(_start): LADDR gp, __global_pointer$ .option pop - /* Init FPU unit if it's there */ + /* Init FPU */ +#ifdef __riscv_flen li t0, MSTATUS_FS csrs mstatus, t0 + csrw fcsr, zero +#endif /* Set exception handler */ LADDR t0, _RISCV_Exception_handler |