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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2016-09-03 03:37:36 +0200
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2016-09-07 20:29:39 +0200
commit4c53be196d7ad9ab9d45c3f8ee5044ddfd46a936 (patch)
tree6a2b89d2492f6297bc4935b950d3875029ef5bd6
parentarm/raspberrypi: include definitions of BCM2836 SMP mailboxes. (diff)
downloadrtems-4c53be196d7ad9ab9d45c3f8ee5044ddfd46a936.tar.bz2
arm/raspberrypi: more definitions of BCM2836 core local peripherals.
-rw-r--r--c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h142
1 files changed, 140 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h b/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h
index 4cedc4cad9..2f42731b35 100644
--- a/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h
+++ b/c/src/lib/libbsp/arm/raspberrypi/include/raspberrypi.h
@@ -347,6 +347,17 @@
/** @} */
/**
+ * @name Raspberry Pi 2 CPU Cores Local Peripherals
+ *
+ * @{
+ */
+
+#define BCM2836_CORE_LOCAL_PERIPH_BASE 0x40000000
+#define BCM2836_CORE_LOCAL_PERIPH_SIZE 0x00040000
+
+/** @} */
+
+/**
* @name Raspberry Pi 2 Mailbox Register Defines
*
* @{
@@ -364,13 +375,140 @@
/** @} */
/**
+ * @name Raspberry Pi 2 Core Timer
+ *
+ * @{
+ */
+
+#define BCM2836_CORE_TIMER_CTRL 0x40000000
+
+#define BCM2836_CORE_TIMER_CTRL_APB_CLK 0x00000100
+#define BCM2836_CORE_TIMER_CTRL_INC_2 0x00000200
+
+#define BCM2836_CORE_TIMER_PRESCALER 0x40000008
+
+#define BCM2836_CORE_TIMER_LS32 0x4000001C
+#define BCM2836_CORE_TIMER_MS32 0x40000020
+
+/** @} */
+
+/**
+ * @name Raspberry Pi 2 Local Timer
+ *
+ * @{
+ */
+
+#define BCM2836_LOCAL_TIMER_CTRL 0x40000034
+
+#define BCM2836_LOCAL_TIMER_CTRL_IRQ_FLAG 0x80000000
+#define BCM2836_LOCAL_TIMER_CTRL_IRQ_EN 0x20000000
+#define BCM2836_LOCAL_TIMER_CTRL_TIMER_EN 0x10000000
+#define BCM2836_LOCAL_TIMER_RELOAD 0x0FFFFFFF
+
+#define BCM2836_LOCAL_TIMER_IRQ_RELOAD 0x40000038
+
+#define BCM2836_LOCAL_TIMER_IRQ_CLEAR 0x80000000
+#define BCM2836_LOCAL_TIMER_RELOAD_NOW 0x40000000
+
+#define BCM2836_LOCAL_TIMER_IRQ_ROUTING 0x40000024
+#define BCM2836_LOCAL_TIMER_ROU_CORE0_IRQ 0x00
+#define BCM2836_LOCAL_TIMER_ROU_CORE1_IRQ 0x01
+#define BCM2836_LOCAL_TIMER_ROU_CORE2_IRQ 0x02
+#define BCM2836_LOCAL_TIMER_ROU_CORE3_IRQ 0x03
+#define BCM2836_LOCAL_TIMER_ROU_CORE0_FIQ 0x04
+#define BCM2836_LOCAL_TIMER_ROU_CORE1_FIQ 0x05
+#define BCM2836_LOCAL_TIMER_ROU_CORE2_FIQ 0x06
+#define BCM2836_LOCAL_TIMER_ROU_CORE3_FIQ 0x07
+
+/** @} */
+
+/**
+ * @name Raspberry Pi 2 IRQ Routing
+ *
+ * @{
+ */
+
+#define BCM2836_GPU_IRQ_ROUTING 0x4000000C
+
+#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE0 0x00000000
+#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE1 0x00000001
+#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE2 0x00000002
+#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE4 0x00000003
+
+#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE0 0x00000000
+#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE1 0x00000004
+#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE2 0x00000008
+#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C
+
+#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C
+
+
+/** @} */
+
+/**
* @name Raspberry Pi 2 Interrupt Register Defines
*
* @{
*/
-#define BCM2836_MAILBOX_IRQ_CTRL_BASE 0x40000050
-#define BCM2836_IRQ_SOURCE_REG_BASE 0x40000060
+/* Timers interrupt control registers */
+#define BCM2836_CORE0_TIMER_IRQ_CTRL_BASE 0x40000040
+#define BCM2836_CORE1_TIMER_IRQ_CTRL_BASE 0x40000044
+#define BCM2836_CORE2_TIMER_IRQ_CTRL_BASE 0x40000048
+#define BCM2836_CORE3_TIMER_IRQ_CTRL_BASE 0x4000004C
+
+#define BCM2836_CORE_TIMER_IRQ_CTRL(cpuidx) \
+ (BCM2836_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
+
+/*
+ * Where to route timer interrupt to, IRQ/FIQ
+ * Setting both the IRQ and FIQ bit gives an FIQ
+ */
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_IRQ 0x01
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_IRQ 0x02
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_IRQ 0x04
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_IRQ 0x08
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_FIQ 0x10
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_FIQ 0x20
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_FIQ 0x40
+#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_FIQ 0x80
+
+/* CPU mailbox registers */
+#define BCM2836_MAILBOX_IRQ_CTRL_BASE 0x40000050
+#define BCM2836_MAILBOX_IRQ_CTRL(cpuidx) \
+ (BCM2836_MAILBOX_IRQ_CTRL_BASE + 0x4 * (cpuidx))
+/*
+ * Where to route mailbox interrupt to, IRQ/FIQ
+ * Setting both the IRQ and FIQ bit gives an FIQ
+ */
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_IRQ 0x01
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_IRQ 0x02
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_IRQ 0x04
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_IRQ 0x08
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_FIQ 0x10
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_FIQ 0x20
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_FIQ 0x40
+#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_FIQ 0x80
+
+#define BCM2836_IRQ_SOURCE_REG_BASE 0x40000060
+#define BCM2836_IRQ_SOURCE_REG(cpuidx) \
+ (BCM2836_IRQ_SOURCE_REG_BASE + 0x4 * (cpuidx))
+
+#define BCM2836_FIQ_SOURCE_REG_BASE 0x40000070
+#define BCM2836_FIQ_SOURCE_REG(cpuidx) \
+ (BCM2836_FIQ_SOURCE_REG_BASE + 0x4 * (cpuidx))
+
+#define BCM2836_IRQ_SOURCE_TIMER0 0x00000001
+#define BCM2836_IRQ_SOURCE_TIMER1 0x00000002
+#define BCM2836_IRQ_SOURCE_TIMER2 0x00000004
+#define BCM2836_IRQ_SOURCE_TIMER3 0x00000008
+#define BCM2836_IRQ_SOURCE_MBOX0 0x00000010
+#define BCM2836_IRQ_SOURCE_MBOX1 0x00000020
+#define BCM2836_IRQ_SOURCE_MBOX2 0x00000040
+#define BCM2836_IRQ_SOURCE_MBOX3 0x00000080
+#define BCM2836_IRQ_SOURCE_GPU 0x00000100
+#define BCM2836_IRQ_SOURCE_PMU 0x00000200
+#define BCM2836_IRQ_SOURCE_LOCAL_TIMER 0x00000800
/** @} */