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| author | Daniel Cederman <cederman@gaisler.com> | 2015-04-22 09:22:27 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-04-22 09:29:56 +0200 |
| commit | 3641320161bdcdae5ca9892078ad21b4efe310ff (patch) | |
| tree | 00bca7cb3c9e36395320ff7df3d0d940fbe153e5 | |
| parent | score: Delete object control block ISR lock (diff) | |
| download | rtems-3641320161bdcdae5ca9892078ad21b4efe310ff.tar.bz2 | |
smptests/smpcache01: Enable interrupts before waiting for other CPUs
Otherwise there is a risk that a CPU misses a cache manager message
from another CPU and the test hangs.
| -rw-r--r-- | testsuites/smptests/smpcache01/init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/testsuites/smptests/smpcache01/init.c b/testsuites/smptests/smpcache01/init.c index 7ad2ef9199..0127a6c907 100644 --- a/testsuites/smptests/smpcache01/init.c +++ b/testsuites/smptests/smpcache01/init.c @@ -120,12 +120,12 @@ static void test_func_isrdisabled_test( size_t set_size, cpu_set_t *cpu_set, _SMP_Multicast_action( set_size, cpu_set, test_cache_message, &ctx ); + _ISR_Enable_without_giant( isr_level ); + _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() ); rtems_test_assert( ctx.count[rtems_get_current_processor()] == rtems_get_processor_count() ); - - _ISR_Enable_without_giant( isr_level ); } static void test_func_giant_taken_test( size_t set_size, cpu_set_t *cpu_set, |