diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-10-11 14:42:55 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-10-11 14:44:47 +0200 |
commit | 271690eb8838f2af30593584a87cb7595bdbdc6b (patch) | |
tree | 990a6fdde8fa37a02ef3aae3951e997a5cda2a62 | |
parent | bsp/qoriq: Add GPIO register map (diff) | |
download | rtems-271690eb8838f2af30593584a87cb7595bdbdc6b.tar.bz2 |
score: Enhance _SMP_barrier_Wait()
Indicate which processor released the barrier. Similar to
pthread_barrier_wait().
-rw-r--r-- | cpukit/score/include/rtems/score/smpbarrier.h | 5 | ||||
-rw-r--r-- | cpukit/score/src/smpbarrierwait.c | 8 |
2 files changed, 11 insertions, 2 deletions
diff --git a/cpukit/score/include/rtems/score/smpbarrier.h b/cpukit/score/include/rtems/score/smpbarrier.h index 8225450b09..fddf7bb1cd 100644 --- a/cpukit/score/include/rtems/score/smpbarrier.h +++ b/cpukit/score/include/rtems/score/smpbarrier.h @@ -106,8 +106,11 @@ static inline void _SMP_barrier_State_initialize( * @param[in, out] control The SMP barrier control. * @param[in, out] state The SMP barrier per-thread state. * @param[in] count The thread count bound to rendezvous. + * + * @retval true This processor performed the barrier release. + * @retval false Otherwise. */ -void _SMP_barrier_Wait( +bool _SMP_barrier_Wait( SMP_barrier_Control *control, SMP_barrier_State *state, unsigned int count diff --git a/cpukit/score/src/smpbarrierwait.c b/cpukit/score/src/smpbarrierwait.c index 5a0de906e4..d06d819273 100644 --- a/cpukit/score/src/smpbarrierwait.c +++ b/cpukit/score/src/smpbarrierwait.c @@ -18,7 +18,7 @@ #include <rtems/score/smpbarrier.h> -void _SMP_barrier_Wait( +bool _SMP_barrier_Wait( SMP_barrier_Control *control, SMP_barrier_State *state, unsigned int count @@ -26,6 +26,7 @@ void _SMP_barrier_Wait( { unsigned int sense = ~state->sense; unsigned int previous_value; + bool performed_release; state->sense = sense; @@ -38,11 +39,16 @@ void _SMP_barrier_Wait( if ( previous_value + 1U == count ) { _Atomic_Store_uint( &control->value, 0U, ATOMIC_ORDER_RELAXED ); _Atomic_Store_uint( &control->sense, sense, ATOMIC_ORDER_RELEASE ); + performed_release = true; } else { while ( _Atomic_Load_uint( &control->sense, ATOMIC_ORDER_ACQUIRE ) != sense ) { /* Wait */ } + + performed_release = false; } + + return performed_release; } |