powerpc: Add up to date CPU_Interrupt_frame

Rename ppc_exc_min_frame to CPU_Interrupt_frame.  Move it and the
corresponding defines to <rtems/score/cpuimpl.h>.

Update #2809.

8 files changed, 399 insertions, 394 deletions

diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/exc-vector-base.S b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/exc-vector-base.S
index b9f0f44ea9..c8103e7e87 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/exc-vector-base.S
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/exc-vector-base.S
@@ -58,7 +58,7 @@ mpc55xx_exc_vector_base:
 	stw	r4, GPR4_OFFSET(r1)
 	li	r4, 4
 	b	ppc_exc_wrap_nopush_std
-	stwu	r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
+	stwu	r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
 	stw	r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
 	li	r4, -32763
@@ -88,7 +88,7 @@ mpc55xx_exc_vector_base:
 	stw	r4, GPR4_OFFSET(r1)
 	li	r4, 24
 	b	ppc_exc_wrap_nopush_std
-	stwu	r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
+	stwu	r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
 	stw	r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
 	li	r4, -32752
@@ -98,7 +98,7 @@ mpc55xx_exc_vector_base:
 	nop
 	nop
 #endif
-	stwu	r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
+	stwu	r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
 	stw	r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
 	li	r4, -32749
diff --git a/c/src/lib/libbsp/powerpc/qoriq/start/start.S b/c/src/lib/libbsp/powerpc/qoriq/start/start.S
index 141812802f..6f6771d672 100644
--- a/c/src/lib/libbsp/powerpc/qoriq/start/start.S
+++ b/c/src/lib/libbsp/powerpc/qoriq/start/start.S
@@ -344,7 +344,7 @@ bsp_exc_vector_base:
 	stw	r4, GPR4_OFFSET(r1)
 	li	r4, 4
 	b	ppc_exc_wrap_nopush_std
-	stwu	r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
+	stwu	r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
 	stw	r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
 	li	r4, -32763
@@ -375,7 +375,7 @@ system_call:
 	stw	r4, GPR4_OFFSET(r1)
 	li	r4, 24
 	b	ppc_exc_wrap_nopush_std
-	stwu	r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
+	stwu	r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
 	stw	r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
 	li	r4, -32752
@@ -385,7 +385,7 @@ system_call:
 	nop
 	nop
 #endif
-	stwu	r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
+	stwu	r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
 	stw	r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
 	li	r4, -32749
diff --git a/c/src/lib/libbsp/powerpc/t32mppc/start/start.S b/c/src/lib/libbsp/powerpc/t32mppc/start/start.S
index 380c019b31..34e1cfac08 100644
--- a/c/src/lib/libbsp/powerpc/t32mppc/start/start.S
+++ b/c/src/lib/libbsp/powerpc/t32mppc/start/start.S
@@ -109,7 +109,7 @@ bsp_exc_vector_base:
 	stw	r4, GPR4_OFFSET(r1)
 	li	r4, 4
 	b	ppc_exc_wrap_nopush_std
-	stwu	r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
+	stwu	r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
 	stw	r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
 	li	r4, -32763
 	b	ppc_exc_wrap_async_normal
@@ -133,11 +133,11 @@ bsp_exc_vector_base:
 	stw	r4, GPR4_OFFSET(r1)
 	li	r4, 24
 	b	ppc_exc_wrap_nopush_std
-	stwu	r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
+	stwu	r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
 	stw	r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
 	li	r4, -32752
 	b	ppc_exc_wrap_async_normal
-	stwu	r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
+	stwu	r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
 	stw	r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
 	li	r4, -32749
 	b	ppc_exc_wrap_async_normal
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S
index 0e71dad93c..c6cbdcec8d 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S
@@ -48,7 +48,7 @@
 
 #ifdef RTEMS_PROFILING
 /*
- * The PPC_EXC_MINIMAL_FRAME_SIZE is enough to store this additional register.
+ * The CPU_INTERRUPT_FRAME_SIZE is enough to store this additional register.
  */
 #define ENTRY_INSTANT_REGISTER r15
 #define ENTRY_INSTANT_OFFSET GPR13_OFFSET
@@ -71,7 +71,7 @@
 
 ppc_exc_min_prolog_async_tmpl_normal:
 
-	stwu	r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
+	stwu	r1, -CPU_INTERRUPT_FRAME_SIZE(r1)
 
 #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
 	stw	VECTOR_REGISTER, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
@@ -468,7 +468,7 @@ thread_dispatching_done:
 #endif /* RTEMS_PROFILING */
 
 	/* Pop stack */
-	addi	r1, r1, PPC_EXC_MINIMAL_FRAME_SIZE
+	addi	r1, r1, CPU_INTERRUPT_FRAME_SIZE
 
 	/* Return */
 	rfi
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
index 54451afe03..4891ddcaa0 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
@@ -27,222 +27,6 @@
 #include <bsp/vectors.h>
 #include <bsp/fatal.h>
 
-#define PPC_EXC_ASSERT_OFFSET(field, off) \
-  RTEMS_STATIC_ASSERT( \
-    offsetof(CPU_Exception_frame, field) + FRAME_LINK_SPACE == off, \
-    CPU_Exception_frame_offset_ ## field \
-  )
-
-#define PPC_EXC_ASSERT_CANONIC_OFFSET(field) \
-  PPC_EXC_ASSERT_OFFSET(field, field ## _OFFSET)
-
-#define PPC_EXC_MIN_ASSERT_OFFSET(field, off) \
-  RTEMS_STATIC_ASSERT( \
-    offsetof(ppc_exc_min_frame, field) + FRAME_LINK_SPACE == off, \
-    ppc_exc_min_frame_offset_ ## field \
-  )
-
-#define PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(field) \
-  PPC_EXC_MIN_ASSERT_OFFSET(field, field ## _OFFSET)
-
-PPC_EXC_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET);
-PPC_EXC_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET);
-PPC_EXC_ASSERT_OFFSET(_EXC_number, EXCEPTION_NUMBER_OFFSET);
-PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CR);
-PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CTR);
-PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_XER);
-PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_LR);
-#ifdef __SPE__
-  PPC_EXC_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET);
-  PPC_EXC_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET);
-#endif
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR0);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR1);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR2);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR3);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR4);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR5);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR6);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR7);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR8);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR9);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR10);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR11);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR12);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR13);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR14);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR15);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR16);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR17);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR18);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR19);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR20);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR21);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR22);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR23);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR24);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR25);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR26);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR27);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR28);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR29);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR30);
-PPC_EXC_ASSERT_CANONIC_OFFSET(GPR31);
-
-PPC_EXC_MIN_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET);
-PPC_EXC_MIN_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_CR);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_CTR);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_XER);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_LR);
-#ifdef __SPE__
-  PPC_EXC_MIN_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET);
-  PPC_EXC_MIN_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET);
-#endif
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR0);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR1);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR2);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR3);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR4);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR5);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR6);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR7);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR8);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR9);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR10);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR11);
-PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR12);
-
-#ifdef PPC_MULTILIB_ALTIVEC
-PPC_EXC_ASSERT_OFFSET(VSCR, PPC_EXC_VSCR_OFFSET);
-PPC_EXC_ASSERT_OFFSET(VRSAVE, PPC_EXC_VRSAVE_OFFSET);
-RTEMS_STATIC_ASSERT(PPC_EXC_VR_OFFSET(0) % 16 == 0, PPC_EXC_VR_OFFSET);
-PPC_EXC_ASSERT_OFFSET(V0, PPC_EXC_VR_OFFSET(0));
-PPC_EXC_ASSERT_OFFSET(V1, PPC_EXC_VR_OFFSET(1));
-PPC_EXC_ASSERT_OFFSET(V2, PPC_EXC_VR_OFFSET(2));
-PPC_EXC_ASSERT_OFFSET(V3, PPC_EXC_VR_OFFSET(3));
-PPC_EXC_ASSERT_OFFSET(V4, PPC_EXC_VR_OFFSET(4));
-PPC_EXC_ASSERT_OFFSET(V5, PPC_EXC_VR_OFFSET(5));
-PPC_EXC_ASSERT_OFFSET(V6, PPC_EXC_VR_OFFSET(6));
-PPC_EXC_ASSERT_OFFSET(V7, PPC_EXC_VR_OFFSET(7));
-PPC_EXC_ASSERT_OFFSET(V8, PPC_EXC_VR_OFFSET(8));
-PPC_EXC_ASSERT_OFFSET(V9, PPC_EXC_VR_OFFSET(9));
-PPC_EXC_ASSERT_OFFSET(V10, PPC_EXC_VR_OFFSET(10));
-PPC_EXC_ASSERT_OFFSET(V11, PPC_EXC_VR_OFFSET(11));
-PPC_EXC_ASSERT_OFFSET(V12, PPC_EXC_VR_OFFSET(12));
-PPC_EXC_ASSERT_OFFSET(V13, PPC_EXC_VR_OFFSET(13));
-PPC_EXC_ASSERT_OFFSET(V14, PPC_EXC_VR_OFFSET(14));
-PPC_EXC_ASSERT_OFFSET(V15, PPC_EXC_VR_OFFSET(15));
-PPC_EXC_ASSERT_OFFSET(V16, PPC_EXC_VR_OFFSET(16));
-PPC_EXC_ASSERT_OFFSET(V17, PPC_EXC_VR_OFFSET(17));
-PPC_EXC_ASSERT_OFFSET(V18, PPC_EXC_VR_OFFSET(18));
-PPC_EXC_ASSERT_OFFSET(V19, PPC_EXC_VR_OFFSET(19));
-PPC_EXC_ASSERT_OFFSET(V20, PPC_EXC_VR_OFFSET(20));
-PPC_EXC_ASSERT_OFFSET(V21, PPC_EXC_VR_OFFSET(21));
-PPC_EXC_ASSERT_OFFSET(V22, PPC_EXC_VR_OFFSET(22));
-PPC_EXC_ASSERT_OFFSET(V23, PPC_EXC_VR_OFFSET(23));
-PPC_EXC_ASSERT_OFFSET(V24, PPC_EXC_VR_OFFSET(24));
-PPC_EXC_ASSERT_OFFSET(V25, PPC_EXC_VR_OFFSET(25));
-PPC_EXC_ASSERT_OFFSET(V26, PPC_EXC_VR_OFFSET(26));
-PPC_EXC_ASSERT_OFFSET(V27, PPC_EXC_VR_OFFSET(27));
-PPC_EXC_ASSERT_OFFSET(V28, PPC_EXC_VR_OFFSET(28));
-PPC_EXC_ASSERT_OFFSET(V29, PPC_EXC_VR_OFFSET(29));
-PPC_EXC_ASSERT_OFFSET(V30, PPC_EXC_VR_OFFSET(30));
-PPC_EXC_ASSERT_OFFSET(V31, PPC_EXC_VR_OFFSET(31));
-
-PPC_EXC_MIN_ASSERT_OFFSET(VSCR, PPC_EXC_MIN_VSCR_OFFSET);
-RTEMS_STATIC_ASSERT(PPC_EXC_MIN_VR_OFFSET(0) % 16 == 0, PPC_EXC_MIN_VR_OFFSET);
-PPC_EXC_MIN_ASSERT_OFFSET(V0, PPC_EXC_MIN_VR_OFFSET(0));
-PPC_EXC_MIN_ASSERT_OFFSET(V1, PPC_EXC_MIN_VR_OFFSET(1));
-PPC_EXC_MIN_ASSERT_OFFSET(V2, PPC_EXC_MIN_VR_OFFSET(2));
-PPC_EXC_MIN_ASSERT_OFFSET(V3, PPC_EXC_MIN_VR_OFFSET(3));
-PPC_EXC_MIN_ASSERT_OFFSET(V4, PPC_EXC_MIN_VR_OFFSET(4));
-PPC_EXC_MIN_ASSERT_OFFSET(V5, PPC_EXC_MIN_VR_OFFSET(5));
-PPC_EXC_MIN_ASSERT_OFFSET(V6, PPC_EXC_MIN_VR_OFFSET(6));
-PPC_EXC_MIN_ASSERT_OFFSET(V7, PPC_EXC_MIN_VR_OFFSET(7));
-PPC_EXC_MIN_ASSERT_OFFSET(V8, PPC_EXC_MIN_VR_OFFSET(8));
-PPC_EXC_MIN_ASSERT_OFFSET(V9, PPC_EXC_MIN_VR_OFFSET(9));
-PPC_EXC_MIN_ASSERT_OFFSET(V10, PPC_EXC_MIN_VR_OFFSET(10));
-PPC_EXC_MIN_ASSERT_OFFSET(V11, PPC_EXC_MIN_VR_OFFSET(11));
-PPC_EXC_MIN_ASSERT_OFFSET(V12, PPC_EXC_MIN_VR_OFFSET(12));
-PPC_EXC_MIN_ASSERT_OFFSET(V13, PPC_EXC_MIN_VR_OFFSET(13));
-PPC_EXC_MIN_ASSERT_OFFSET(V14, PPC_EXC_MIN_VR_OFFSET(14));
-PPC_EXC_MIN_ASSERT_OFFSET(V15, PPC_EXC_MIN_VR_OFFSET(15));
-PPC_EXC_MIN_ASSERT_OFFSET(V16, PPC_EXC_MIN_VR_OFFSET(16));
-PPC_EXC_MIN_ASSERT_OFFSET(V17, PPC_EXC_MIN_VR_OFFSET(17));
-PPC_EXC_MIN_ASSERT_OFFSET(V18, PPC_EXC_MIN_VR_OFFSET(18));
-PPC_EXC_MIN_ASSERT_OFFSET(V19, PPC_EXC_MIN_VR_OFFSET(19));
-#endif
-
-#ifdef PPC_MULTILIB_FPU
-RTEMS_STATIC_ASSERT(PPC_EXC_FR_OFFSET(0) % 8 == 0, PPC_EXC_FR_OFFSET);
-PPC_EXC_ASSERT_OFFSET(F0, PPC_EXC_FR_OFFSET(0));
-PPC_EXC_ASSERT_OFFSET(F1, PPC_EXC_FR_OFFSET(1));
-PPC_EXC_ASSERT_OFFSET(F2, PPC_EXC_FR_OFFSET(2));
-PPC_EXC_ASSERT_OFFSET(F3, PPC_EXC_FR_OFFSET(3));
-PPC_EXC_ASSERT_OFFSET(F4, PPC_EXC_FR_OFFSET(4));
-PPC_EXC_ASSERT_OFFSET(F5, PPC_EXC_FR_OFFSET(5));
-PPC_EXC_ASSERT_OFFSET(F6, PPC_EXC_FR_OFFSET(6));
-PPC_EXC_ASSERT_OFFSET(F7, PPC_EXC_FR_OFFSET(7));
-PPC_EXC_ASSERT_OFFSET(F8, PPC_EXC_FR_OFFSET(8));
-PPC_EXC_ASSERT_OFFSET(F9, PPC_EXC_FR_OFFSET(9));
-PPC_EXC_ASSERT_OFFSET(F10, PPC_EXC_FR_OFFSET(10));
-PPC_EXC_ASSERT_OFFSET(F11, PPC_EXC_FR_OFFSET(11));
-PPC_EXC_ASSERT_OFFSET(F12, PPC_EXC_FR_OFFSET(12));
-PPC_EXC_ASSERT_OFFSET(F13, PPC_EXC_FR_OFFSET(13));
-PPC_EXC_ASSERT_OFFSET(F14, PPC_EXC_FR_OFFSET(14));
-PPC_EXC_ASSERT_OFFSET(F15, PPC_EXC_FR_OFFSET(15));
-PPC_EXC_ASSERT_OFFSET(F16, PPC_EXC_FR_OFFSET(16));
-PPC_EXC_ASSERT_OFFSET(F17, PPC_EXC_FR_OFFSET(17));
-PPC_EXC_ASSERT_OFFSET(F18, PPC_EXC_FR_OFFSET(18));
-PPC_EXC_ASSERT_OFFSET(F19, PPC_EXC_FR_OFFSET(19));
-PPC_EXC_ASSERT_OFFSET(F20, PPC_EXC_FR_OFFSET(20));
-PPC_EXC_ASSERT_OFFSET(F21, PPC_EXC_FR_OFFSET(21));
-PPC_EXC_ASSERT_OFFSET(F22, PPC_EXC_FR_OFFSET(22));
-PPC_EXC_ASSERT_OFFSET(F23, PPC_EXC_FR_OFFSET(23));
-PPC_EXC_ASSERT_OFFSET(F24, PPC_EXC_FR_OFFSET(24));
-PPC_EXC_ASSERT_OFFSET(F25, PPC_EXC_FR_OFFSET(25));
-PPC_EXC_ASSERT_OFFSET(F26, PPC_EXC_FR_OFFSET(26));
-PPC_EXC_ASSERT_OFFSET(F27, PPC_EXC_FR_OFFSET(27));
-PPC_EXC_ASSERT_OFFSET(F28, PPC_EXC_FR_OFFSET(28));
-PPC_EXC_ASSERT_OFFSET(F29, PPC_EXC_FR_OFFSET(29));
-PPC_EXC_ASSERT_OFFSET(F30, PPC_EXC_FR_OFFSET(30));
-PPC_EXC_ASSERT_OFFSET(F31, PPC_EXC_FR_OFFSET(31));
-PPC_EXC_ASSERT_OFFSET(FPSCR, PPC_EXC_FPSCR_OFFSET);
-
-RTEMS_STATIC_ASSERT(PPC_EXC_MIN_FR_OFFSET(0) % 8 == 0, PPC_EXC_MIN_FR_OFFSET);
-PPC_EXC_MIN_ASSERT_OFFSET(F0, PPC_EXC_MIN_FR_OFFSET(0));
-PPC_EXC_MIN_ASSERT_OFFSET(F1, PPC_EXC_MIN_FR_OFFSET(1));
-PPC_EXC_MIN_ASSERT_OFFSET(F2, PPC_EXC_MIN_FR_OFFSET(2));
-PPC_EXC_MIN_ASSERT_OFFSET(F3, PPC_EXC_MIN_FR_OFFSET(3));
-PPC_EXC_MIN_ASSERT_OFFSET(F4, PPC_EXC_MIN_FR_OFFSET(4));
-PPC_EXC_MIN_ASSERT_OFFSET(F5, PPC_EXC_MIN_FR_OFFSET(5));
-PPC_EXC_MIN_ASSERT_OFFSET(F6, PPC_EXC_MIN_FR_OFFSET(6));
-PPC_EXC_MIN_ASSERT_OFFSET(F7, PPC_EXC_MIN_FR_OFFSET(7));
-PPC_EXC_MIN_ASSERT_OFFSET(F8, PPC_EXC_MIN_FR_OFFSET(8));
-PPC_EXC_MIN_ASSERT_OFFSET(F9, PPC_EXC_MIN_FR_OFFSET(9));
-PPC_EXC_MIN_ASSERT_OFFSET(F10, PPC_EXC_MIN_FR_OFFSET(10));
-PPC_EXC_MIN_ASSERT_OFFSET(F11, PPC_EXC_MIN_FR_OFFSET(11));
-PPC_EXC_MIN_ASSERT_OFFSET(F12, PPC_EXC_MIN_FR_OFFSET(12));
-PPC_EXC_MIN_ASSERT_OFFSET(F13, PPC_EXC_MIN_FR_OFFSET(13));
-PPC_EXC_MIN_ASSERT_OFFSET(FPSCR, PPC_EXC_MIN_FPSCR_OFFSET);
-#endif
-
-RTEMS_STATIC_ASSERT(
-  PPC_EXC_MINIMAL_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0,
-  PPC_EXC_MINIMAL_FRAME_SIZE
-);
-
-RTEMS_STATIC_ASSERT(
-  PPC_EXC_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0,
-  PPC_EXC_FRAME_SIZE
-);
-
-RTEMS_STATIC_ASSERT(
-  sizeof(CPU_Exception_frame) + FRAME_LINK_SPACE <= PPC_EXC_FRAME_SIZE,
-  CPU_Exception_frame
-);
-
 uint32_t ppc_exc_cache_wb_check = 1;
 
 #define MTIVPR(prefix) __asm__ volatile ("mtivpr %0" : : "r" (prefix))
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
index f45c8338a2..7835abb7e4 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
@@ -36,7 +36,7 @@
 #define LIBCPU_VECTORS_H
 
 #include <bspopts.h>
-
+#include <rtems/score/cpuimpl.h>
 #include <libcpu/powerpc-utility.h>
 
 #ifdef __cplusplus
@@ -143,49 +143,6 @@ extern "C" {
 
 /** @} */
 
-#ifndef __SPE__
-  #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 36)
-  #define PPC_EXC_VECTOR_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(4)
-  #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU)
-    #define PPC_EXC_VRSAVE_OFFSET 168
-    #define PPC_EXC_VSCR_OFFSET 172
-    #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + 176)
-    #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + 688)
-    #define PPC_EXC_FPSCR_OFFSET 944
-    #define PPC_EXC_FRAME_SIZE 960
-    #define PPC_EXC_MIN_VSCR_OFFSET 92
-    #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + 96)
-    #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + 416)
-    #define PPC_EXC_MIN_FPSCR_OFFSET 528
-    #define PPC_EXC_MINIMAL_FRAME_SIZE 544
-  #elif defined(PPC_MULTILIB_ALTIVEC)
-    #define PPC_EXC_VRSAVE_OFFSET 168
-    #define PPC_EXC_VSCR_OFFSET 172
-    #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + 176)
-    #define PPC_EXC_FRAME_SIZE 688
-    #define PPC_EXC_MIN_VSCR_OFFSET 92
-    #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + 96)
-    #define PPC_EXC_MINIMAL_FRAME_SIZE 416
-  #elif defined(PPC_MULTILIB_FPU)
-    #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + 168)
-    #define PPC_EXC_FPSCR_OFFSET 424
-    #define PPC_EXC_FRAME_SIZE 448
-    #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + 96)
-    #define PPC_EXC_MIN_FPSCR_OFFSET 92
-    #define PPC_EXC_MINIMAL_FRAME_SIZE 224
-  #else
-    #define PPC_EXC_FRAME_SIZE 176
-    #define PPC_EXC_MINIMAL_FRAME_SIZE 96
-  #endif
-#else
-  #define PPC_EXC_SPEFSCR_OFFSET 36
-  #define PPC_EXC_ACC_OFFSET 40
-  #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 48)
-  #define PPC_EXC_VECTOR_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(4) + 4)
-  #define PPC_EXC_MINIMAL_FRAME_SIZE 160
-  #define PPC_EXC_FRAME_SIZE 320
-#endif
-
 /**
  * @defgroup ppc_exc_frame PowerPC Exception Frame
  *
@@ -201,46 +158,6 @@ extern "C" {
  */
 #define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
 
-#define SRR0_FRAME_OFFSET 8
-#define SRR1_FRAME_OFFSET 12
-#define EXCEPTION_NUMBER_OFFSET 16
-#define EXC_CR_OFFSET 20
-#define EXC_CTR_OFFSET 24
-#define EXC_XER_OFFSET 28
-#define EXC_LR_OFFSET 32
-#define GPR0_OFFSET PPC_EXC_GPR_OFFSET(0)
-#define GPR1_OFFSET PPC_EXC_GPR_OFFSET(1)
-#define GPR2_OFFSET PPC_EXC_GPR_OFFSET(2)
-#define GPR3_OFFSET PPC_EXC_GPR_OFFSET(3)
-#define GPR4_OFFSET PPC_EXC_GPR_OFFSET(4)
-#define GPR5_OFFSET PPC_EXC_GPR_OFFSET(5)
-#define GPR6_OFFSET PPC_EXC_GPR_OFFSET(6)
-#define GPR7_OFFSET PPC_EXC_GPR_OFFSET(7)
-#define GPR8_OFFSET PPC_EXC_GPR_OFFSET(8)
-#define GPR9_OFFSET PPC_EXC_GPR_OFFSET(9)
-#define GPR10_OFFSET PPC_EXC_GPR_OFFSET(10)
-#define GPR11_OFFSET PPC_EXC_GPR_OFFSET(11)
-#define GPR12_OFFSET PPC_EXC_GPR_OFFSET(12)
-#define GPR13_OFFSET PPC_EXC_GPR_OFFSET(13)
-#define GPR14_OFFSET PPC_EXC_GPR_OFFSET(14)
-#define GPR15_OFFSET PPC_EXC_GPR_OFFSET(15)
-#define GPR16_OFFSET PPC_EXC_GPR_OFFSET(16)
-#define GPR17_OFFSET PPC_EXC_GPR_OFFSET(17)
-#define GPR18_OFFSET PPC_EXC_GPR_OFFSET(18)
-#define GPR19_OFFSET PPC_EXC_GPR_OFFSET(19)
-#define GPR20_OFFSET PPC_EXC_GPR_OFFSET(20)
-#define GPR21_OFFSET PPC_EXC_GPR_OFFSET(21)
-#define GPR22_OFFSET PPC_EXC_GPR_OFFSET(22)
-#define GPR23_OFFSET PPC_EXC_GPR_OFFSET(23)
-#define GPR24_OFFSET PPC_EXC_GPR_OFFSET(24)
-#define GPR25_OFFSET PPC_EXC_GPR_OFFSET(25)
-#define GPR26_OFFSET PPC_EXC_GPR_OFFSET(26)
-#define GPR27_OFFSET PPC_EXC_GPR_OFFSET(27)
-#define GPR28_OFFSET PPC_EXC_GPR_OFFSET(28)
-#define GPR29_OFFSET PPC_EXC_GPR_OFFSET(29)
-#define GPR30_OFFSET PPC_EXC_GPR_OFFSET(30)
-#define GPR31_OFFSET PPC_EXC_GPR_OFFSET(31)
-
 #define EXC_GENERIC_SIZE PPC_EXC_FRAME_SIZE
 
 #if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC)
@@ -257,9 +174,6 @@ extern "C" {
 #define EXC_VEC_SIZE   (0)
 #endif
 
-/* Exception stack frame -> BSP_Exception_frame */
-#define FRAME_LINK_SPACE 8
-
 /*
  * maintain the EABI requested 8 bytes aligment
  * As SVR4 ABI requires 16, make it 16 (as some
@@ -277,79 +191,6 @@ extern "C" {
  * @{
  */
 
-typedef struct {
-  uint32_t EXC_SRR0;
-  uint32_t EXC_SRR1;
-  uint32_t unused;
-  uint32_t EXC_CR;
-  uint32_t EXC_CTR;
-  uint32_t EXC_XER;
-  uint32_t EXC_LR;
-  #ifdef __SPE__
-    uint32_t EXC_SPEFSCR;
-    uint64_t EXC_ACC;
-  #endif
-  PPC_GPR_TYPE GPR0;
-  PPC_GPR_TYPE GPR1;
-  PPC_GPR_TYPE GPR2;
-  PPC_GPR_TYPE GPR3;
-  PPC_GPR_TYPE GPR4;
-  PPC_GPR_TYPE GPR5;
-  PPC_GPR_TYPE GPR6;
-  PPC_GPR_TYPE GPR7;
-  PPC_GPR_TYPE GPR8;
-  PPC_GPR_TYPE GPR9;
-  PPC_GPR_TYPE GPR10;
-  PPC_GPR_TYPE GPR11;
-  PPC_GPR_TYPE GPR12;
-  uint32_t EARLY_INSTANT;
-  #ifdef PPC_MULTILIB_ALTIVEC
-    /* This field must take stvewx/lvewx requirements into account */
-    uint32_t VSCR;
-
-    uint8_t V0[16];
-    uint8_t V1[16];
-    uint8_t V2[16];
-    uint8_t V3[16];
-    uint8_t V4[16];
-    uint8_t V5[16];
-    uint8_t V6[16];
-    uint8_t V7[16];
-    uint8_t V8[16];
-    uint8_t V9[16];
-    uint8_t V10[16];
-    uint8_t V11[16];
-    uint8_t V12[16];
-    uint8_t V13[16];
-    uint8_t V14[16];
-    uint8_t V15[16];
-    uint8_t V16[16];
-    uint8_t V17[16];
-    uint8_t V18[16];
-    uint8_t V19[16];
-  #endif
-  #ifdef PPC_MULTILIB_FPU
-    #ifndef PPC_MULTILIB_ALTIVEC
-      uint32_t reserved_for_alignment;
-    #endif
-    double F0;
-    double F1;
-    double F2;
-    double F3;
-    double F4;
-    double F5;
-    double F6;
-    double F7;
-    double F8;
-    double F9;
-    double F10;
-    double F11;
-    double F12;
-    double F13;
-    uint64_t FPSCR;
-  #endif
-} ppc_exc_min_frame;
-
 typedef CPU_Exception_frame BSP_Exception_frame;
 
 /** @} */
diff --git a/cpukit/score/cpu/powerpc/cpu.c b/cpukit/score/cpu/powerpc/cpu.c
index 5383a8ee24..fafc9a686b 100644
--- a/cpukit/score/cpu/powerpc/cpu.c
+++ b/cpukit/score/cpu/powerpc/cpu.c
@@ -5,9 +5,11 @@
  */
 
 /*
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
+ * Copyright (C) 2009, 2016 embedded brains GmbH.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
  */
 
 /*
@@ -19,8 +21,7 @@
   #include "config.h"
 #endif
 
-#include <rtems/system.h>
-#include <rtems/score/cpu.h>
+#include <rtems/score/cpuimpl.h>
 
 #define PPC_ASSERT_OFFSET(field, off) \
   RTEMS_STATIC_ASSERT( \
@@ -102,3 +103,219 @@ RTEMS_STATIC_ASSERT(
   sizeof(Context_Control) % PPC_DEFAULT_CACHE_LINE_SIZE == 0,
   ppc_context_size
 );
+
+#define PPC_EXC_ASSERT_OFFSET(field, off) \
+  RTEMS_STATIC_ASSERT( \
+    offsetof(CPU_Exception_frame, field) + FRAME_LINK_SPACE == off, \
+    CPU_Exception_frame_offset_ ## field \
+  )
+
+#define PPC_EXC_ASSERT_CANONIC_OFFSET(field) \
+  PPC_EXC_ASSERT_OFFSET(field, field ## _OFFSET)
+
+#define PPC_EXC_MIN_ASSERT_OFFSET(field, off) \
+  RTEMS_STATIC_ASSERT( \
+    offsetof(CPU_Interrupt_frame, field) == off, \
+    CPU_Interrupt_frame_offset_ ## field \
+  )
+
+#define PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(field) \
+  PPC_EXC_MIN_ASSERT_OFFSET(field, field ## _OFFSET)
+
+PPC_EXC_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET);
+PPC_EXC_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET);
+PPC_EXC_ASSERT_OFFSET(_EXC_number, EXCEPTION_NUMBER_OFFSET);
+PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CR);
+PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CTR);
+PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_XER);
+PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_LR);
+#ifdef __SPE__
+  PPC_EXC_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET);
+  PPC_EXC_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET);
+#endif
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR0);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR1);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR2);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR3);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR4);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR5);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR6);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR7);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR8);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR9);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR10);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR11);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR12);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR13);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR14);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR15);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR16);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR17);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR18);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR19);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR20);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR21);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR22);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR23);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR24);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR25);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR26);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR27);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR28);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR29);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR30);
+PPC_EXC_ASSERT_CANONIC_OFFSET(GPR31);
+
+PPC_EXC_MIN_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET);
+PPC_EXC_MIN_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_CR);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_CTR);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_XER);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_LR);
+#ifdef __SPE__
+  PPC_EXC_MIN_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET);
+  PPC_EXC_MIN_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET);
+#endif
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR0);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR1);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR2);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR3);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR4);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR5);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR6);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR7);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR8);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR9);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR10);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR11);
+PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR12);
+
+#ifdef PPC_MULTILIB_ALTIVEC
+PPC_EXC_ASSERT_OFFSET(VSCR, PPC_EXC_VSCR_OFFSET);
+PPC_EXC_ASSERT_OFFSET(VRSAVE, PPC_EXC_VRSAVE_OFFSET);
+RTEMS_STATIC_ASSERT(PPC_EXC_VR_OFFSET(0) % 16 == 0, PPC_EXC_VR_OFFSET);
+PPC_EXC_ASSERT_OFFSET(V0, PPC_EXC_VR_OFFSET(0));
+PPC_EXC_ASSERT_OFFSET(V1, PPC_EXC_VR_OFFSET(1));
+PPC_EXC_ASSERT_OFFSET(V2, PPC_EXC_VR_OFFSET(2));
+PPC_EXC_ASSERT_OFFSET(V3, PPC_EXC_VR_OFFSET(3));
+PPC_EXC_ASSERT_OFFSET(V4, PPC_EXC_VR_OFFSET(4));
+PPC_EXC_ASSERT_OFFSET(V5, PPC_EXC_VR_OFFSET(5));
+PPC_EXC_ASSERT_OFFSET(V6, PPC_EXC_VR_OFFSET(6));
+PPC_EXC_ASSERT_OFFSET(V7, PPC_EXC_VR_OFFSET(7));
+PPC_EXC_ASSERT_OFFSET(V8, PPC_EXC_VR_OFFSET(8));
+PPC_EXC_ASSERT_OFFSET(V9, PPC_EXC_VR_OFFSET(9));
+PPC_EXC_ASSERT_OFFSET(V10, PPC_EXC_VR_OFFSET(10));
+PPC_EXC_ASSERT_OFFSET(V11, PPC_EXC_VR_OFFSET(11));
+PPC_EXC_ASSERT_OFFSET(V12, PPC_EXC_VR_OFFSET(12));
+PPC_EXC_ASSERT_OFFSET(V13, PPC_EXC_VR_OFFSET(13));
+PPC_EXC_ASSERT_OFFSET(V14, PPC_EXC_VR_OFFSET(14));
+PPC_EXC_ASSERT_OFFSET(V15, PPC_EXC_VR_OFFSET(15));
+PPC_EXC_ASSERT_OFFSET(V16, PPC_EXC_VR_OFFSET(16));
+PPC_EXC_ASSERT_OFFSET(V17, PPC_EXC_VR_OFFSET(17));
+PPC_EXC_ASSERT_OFFSET(V18, PPC_EXC_VR_OFFSET(18));
+PPC_EXC_ASSERT_OFFSET(V19, PPC_EXC_VR_OFFSET(19));
+PPC_EXC_ASSERT_OFFSET(V20, PPC_EXC_VR_OFFSET(20));
+PPC_EXC_ASSERT_OFFSET(V21, PPC_EXC_VR_OFFSET(21));
+PPC_EXC_ASSERT_OFFSET(V22, PPC_EXC_VR_OFFSET(22));
+PPC_EXC_ASSERT_OFFSET(V23, PPC_EXC_VR_OFFSET(23));
+PPC_EXC_ASSERT_OFFSET(V24, PPC_EXC_VR_OFFSET(24));
+PPC_EXC_ASSERT_OFFSET(V25, PPC_EXC_VR_OFFSET(25));
+PPC_EXC_ASSERT_OFFSET(V26, PPC_EXC_VR_OFFSET(26));
+PPC_EXC_ASSERT_OFFSET(V27, PPC_EXC_VR_OFFSET(27));
+PPC_EXC_ASSERT_OFFSET(V28, PPC_EXC_VR_OFFSET(28));
+PPC_EXC_ASSERT_OFFSET(V29, PPC_EXC_VR_OFFSET(29));
+PPC_EXC_ASSERT_OFFSET(V30, PPC_EXC_VR_OFFSET(30));
+PPC_EXC_ASSERT_OFFSET(V31, PPC_EXC_VR_OFFSET(31));
+
+PPC_EXC_MIN_ASSERT_OFFSET(VSCR, PPC_EXC_MIN_VSCR_OFFSET);
+RTEMS_STATIC_ASSERT(PPC_EXC_MIN_VR_OFFSET(0) % 16 == 0, PPC_EXC_MIN_VR_OFFSET);
+PPC_EXC_MIN_ASSERT_OFFSET(V0, PPC_EXC_MIN_VR_OFFSET(0));
+PPC_EXC_MIN_ASSERT_OFFSET(V1, PPC_EXC_MIN_VR_OFFSET(1));
+PPC_EXC_MIN_ASSERT_OFFSET(V2, PPC_EXC_MIN_VR_OFFSET(2));
+PPC_EXC_MIN_ASSERT_OFFSET(V3, PPC_EXC_MIN_VR_OFFSET(3));
+PPC_EXC_MIN_ASSERT_OFFSET(V4, PPC_EXC_MIN_VR_OFFSET(4));
+PPC_EXC_MIN_ASSERT_OFFSET(V5, PPC_EXC_MIN_VR_OFFSET(5));
+PPC_EXC_MIN_ASSERT_OFFSET(V6, PPC_EXC_MIN_VR_OFFSET(6));
+PPC_EXC_MIN_ASSERT_OFFSET(V7, PPC_EXC_MIN_VR_OFFSET(7));
+PPC_EXC_MIN_ASSERT_OFFSET(V8, PPC_EXC_MIN_VR_OFFSET(8));
+PPC_EXC_MIN_ASSERT_OFFSET(V9, PPC_EXC_MIN_VR_OFFSET(9));
+PPC_EXC_MIN_ASSERT_OFFSET(V10, PPC_EXC_MIN_VR_OFFSET(10));
+PPC_EXC_MIN_ASSERT_OFFSET(V11, PPC_EXC_MIN_VR_OFFSET(11));
+PPC_EXC_MIN_ASSERT_OFFSET(V12, PPC_EXC_MIN_VR_OFFSET(12));
+PPC_EXC_MIN_ASSERT_OFFSET(V13, PPC_EXC_MIN_VR_OFFSET(13));
+PPC_EXC_MIN_ASSERT_OFFSET(V14, PPC_EXC_MIN_VR_OFFSET(14));
+PPC_EXC_MIN_ASSERT_OFFSET(V15, PPC_EXC_MIN_VR_OFFSET(15));
+PPC_EXC_MIN_ASSERT_OFFSET(V16, PPC_EXC_MIN_VR_OFFSET(16));
+PPC_EXC_MIN_ASSERT_OFFSET(V17, PPC_EXC_MIN_VR_OFFSET(17));
+PPC_EXC_MIN_ASSERT_OFFSET(V18, PPC_EXC_MIN_VR_OFFSET(18));
+PPC_EXC_MIN_ASSERT_OFFSET(V19, PPC_EXC_MIN_VR_OFFSET(19));
+#endif
+
+#ifdef PPC_MULTILIB_FPU
+RTEMS_STATIC_ASSERT(PPC_EXC_FR_OFFSET(0) % 8 == 0, PPC_EXC_FR_OFFSET);
+PPC_EXC_ASSERT_OFFSET(F0, PPC_EXC_FR_OFFSET(0));
+PPC_EXC_ASSERT_OFFSET(F1, PPC_EXC_FR_OFFSET(1));
+PPC_EXC_ASSERT_OFFSET(F2, PPC_EXC_FR_OFFSET(2));
+PPC_EXC_ASSERT_OFFSET(F3, PPC_EXC_FR_OFFSET(3));
+PPC_EXC_ASSERT_OFFSET(F4, PPC_EXC_FR_OFFSET(4));
+PPC_EXC_ASSERT_OFFSET(F5, PPC_EXC_FR_OFFSET(5));
+PPC_EXC_ASSERT_OFFSET(F6, PPC_EXC_FR_OFFSET(6));
+PPC_EXC_ASSERT_OFFSET(F7, PPC_EXC_FR_OFFSET(7));
+PPC_EXC_ASSERT_OFFSET(F8, PPC_EXC_FR_OFFSET(8));
+PPC_EXC_ASSERT_OFFSET(F9, PPC_EXC_FR_OFFSET(9));
+PPC_EXC_ASSERT_OFFSET(F10, PPC_EXC_FR_OFFSET(10));
+PPC_EXC_ASSERT_OFFSET(F11, PPC_EXC_FR_OFFSET(11));
+PPC_EXC_ASSERT_OFFSET(F12, PPC_EXC_FR_OFFSET(12));
+PPC_EXC_ASSERT_OFFSET(F13, PPC_EXC_FR_OFFSET(13));
+PPC_EXC_ASSERT_OFFSET(F14, PPC_EXC_FR_OFFSET(14));
+PPC_EXC_ASSERT_OFFSET(F15, PPC_EXC_FR_OFFSET(15));
+PPC_EXC_ASSERT_OFFSET(F16, PPC_EXC_FR_OFFSET(16));
+PPC_EXC_ASSERT_OFFSET(F17, PPC_EXC_FR_OFFSET(17));
+PPC_EXC_ASSERT_OFFSET(F18, PPC_EXC_FR_OFFSET(18));
+PPC_EXC_ASSERT_OFFSET(F19, PPC_EXC_FR_OFFSET(19));
+PPC_EXC_ASSERT_OFFSET(F20, PPC_EXC_FR_OFFSET(20));
+PPC_EXC_ASSERT_OFFSET(F21, PPC_EXC_FR_OFFSET(21));
+PPC_EXC_ASSERT_OFFSET(F22, PPC_EXC_FR_OFFSET(22));
+PPC_EXC_ASSERT_OFFSET(F23, PPC_EXC_FR_OFFSET(23));
+PPC_EXC_ASSERT_OFFSET(F24, PPC_EXC_FR_OFFSET(24));
+PPC_EXC_ASSERT_OFFSET(F25, PPC_EXC_FR_OFFSET(25));
+PPC_EXC_ASSERT_OFFSET(F26, PPC_EXC_FR_OFFSET(26));
+PPC_EXC_ASSERT_OFFSET(F27, PPC_EXC_FR_OFFSET(27));
+PPC_EXC_ASSERT_OFFSET(F28, PPC_EXC_FR_OFFSET(28));
+PPC_EXC_ASSERT_OFFSET(F29, PPC_EXC_FR_OFFSET(29));
+PPC_EXC_ASSERT_OFFSET(F30, PPC_EXC_FR_OFFSET(30));
+PPC_EXC_ASSERT_OFFSET(F31, PPC_EXC_FR_OFFSET(31));
+PPC_EXC_ASSERT_OFFSET(FPSCR, PPC_EXC_FPSCR_OFFSET);
+
+RTEMS_STATIC_ASSERT(PPC_EXC_MIN_FR_OFFSET(0) % 8 == 0, PPC_EXC_MIN_FR_OFFSET);
+PPC_EXC_MIN_ASSERT_OFFSET(F0, PPC_EXC_MIN_FR_OFFSET(0));
+PPC_EXC_MIN_ASSERT_OFFSET(F1, PPC_EXC_MIN_FR_OFFSET(1));
+PPC_EXC_MIN_ASSERT_OFFSET(F2, PPC_EXC_MIN_FR_OFFSET(2));
+PPC_EXC_MIN_ASSERT_OFFSET(F3, PPC_EXC_MIN_FR_OFFSET(3));
+PPC_EXC_MIN_ASSERT_OFFSET(F4, PPC_EXC_MIN_FR_OFFSET(4));
+PPC_EXC_MIN_ASSERT_OFFSET(F5, PPC_EXC_MIN_FR_OFFSET(5));
+PPC_EXC_MIN_ASSERT_OFFSET(F6, PPC_EXC_MIN_FR_OFFSET(6));
+PPC_EXC_MIN_ASSERT_OFFSET(F7, PPC_EXC_MIN_FR_OFFSET(7));
+PPC_EXC_MIN_ASSERT_OFFSET(F8, PPC_EXC_MIN_FR_OFFSET(8));
+PPC_EXC_MIN_ASSERT_OFFSET(F9, PPC_EXC_MIN_FR_OFFSET(9));
+PPC_EXC_MIN_ASSERT_OFFSET(F10, PPC_EXC_MIN_FR_OFFSET(10));
+PPC_EXC_MIN_ASSERT_OFFSET(F11, PPC_EXC_MIN_FR_OFFSET(11));
+PPC_EXC_MIN_ASSERT_OFFSET(F12, PPC_EXC_MIN_FR_OFFSET(12));
+PPC_EXC_MIN_ASSERT_OFFSET(F13, PPC_EXC_MIN_FR_OFFSET(13));
+PPC_EXC_MIN_ASSERT_OFFSET(FPSCR, PPC_EXC_MIN_FPSCR_OFFSET);
+#endif
+
+RTEMS_STATIC_ASSERT(
+  CPU_INTERRUPT_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0,
+  CPU_INTERRUPT_FRAME_SIZE
+);
+
+RTEMS_STATIC_ASSERT(
+  PPC_EXC_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0,
+  PPC_EXC_FRAME_SIZE
+);
+
+RTEMS_STATIC_ASSERT(
+  sizeof(CPU_Exception_frame) + FRAME_LINK_SPACE <= PPC_EXC_FRAME_SIZE,
+  CPU_Exception_frame
+);
diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h b/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h
index a3761d28d7..bc03ab98ac 100644
--- a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h
@@ -5,7 +5,12 @@
  */
 
 /*
- * Copyright (c) 2013, 2016 embedded brains GmbH
+ * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
+ *                    Canon Centre Recherche France.
+ *
+ * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
+ *
+ * Copyright (c) 2009, 2016 embedded brains GmbH
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -17,6 +22,92 @@
 
 #include <rtems/score/cpu.h>
 
+#define SRR0_FRAME_OFFSET 8
+#define SRR1_FRAME_OFFSET 12
+#define EXCEPTION_NUMBER_OFFSET 16
+#define EXC_CR_OFFSET 20
+#define EXC_CTR_OFFSET 24
+#define EXC_XER_OFFSET 28
+#define EXC_LR_OFFSET 32
+#define GPR0_OFFSET PPC_EXC_GPR_OFFSET(0)
+#define GPR1_OFFSET PPC_EXC_GPR_OFFSET(1)
+#define GPR2_OFFSET PPC_EXC_GPR_OFFSET(2)
+#define GPR3_OFFSET PPC_EXC_GPR_OFFSET(3)
+#define GPR4_OFFSET PPC_EXC_GPR_OFFSET(4)
+#define GPR5_OFFSET PPC_EXC_GPR_OFFSET(5)
+#define GPR6_OFFSET PPC_EXC_GPR_OFFSET(6)
+#define GPR7_OFFSET PPC_EXC_GPR_OFFSET(7)
+#define GPR8_OFFSET PPC_EXC_GPR_OFFSET(8)
+#define GPR9_OFFSET PPC_EXC_GPR_OFFSET(9)
+#define GPR10_OFFSET PPC_EXC_GPR_OFFSET(10)
+#define GPR11_OFFSET PPC_EXC_GPR_OFFSET(11)
+#define GPR12_OFFSET PPC_EXC_GPR_OFFSET(12)
+#define GPR13_OFFSET PPC_EXC_GPR_OFFSET(13)
+#define GPR14_OFFSET PPC_EXC_GPR_OFFSET(14)
+#define GPR15_OFFSET PPC_EXC_GPR_OFFSET(15)
+#define GPR16_OFFSET PPC_EXC_GPR_OFFSET(16)
+#define GPR17_OFFSET PPC_EXC_GPR_OFFSET(17)
+#define GPR18_OFFSET PPC_EXC_GPR_OFFSET(18)
+#define GPR19_OFFSET PPC_EXC_GPR_OFFSET(19)
+#define GPR20_OFFSET PPC_EXC_GPR_OFFSET(20)
+#define GPR21_OFFSET PPC_EXC_GPR_OFFSET(21)
+#define GPR22_OFFSET PPC_EXC_GPR_OFFSET(22)
+#define GPR23_OFFSET PPC_EXC_GPR_OFFSET(23)
+#define GPR24_OFFSET PPC_EXC_GPR_OFFSET(24)
+#define GPR25_OFFSET PPC_EXC_GPR_OFFSET(25)
+#define GPR26_OFFSET PPC_EXC_GPR_OFFSET(26)
+#define GPR27_OFFSET PPC_EXC_GPR_OFFSET(27)
+#define GPR28_OFFSET PPC_EXC_GPR_OFFSET(28)
+#define GPR29_OFFSET PPC_EXC_GPR_OFFSET(29)
+#define GPR30_OFFSET PPC_EXC_GPR_OFFSET(30)
+#define GPR31_OFFSET PPC_EXC_GPR_OFFSET(31)
+
+/* Exception stack frame -> BSP_Exception_frame */
+#define FRAME_LINK_SPACE 8
+
+#ifndef __SPE__
+  #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 36)
+  #define PPC_EXC_VECTOR_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(4)
+  #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU)
+    #define PPC_EXC_VRSAVE_OFFSET 168
+    #define PPC_EXC_VSCR_OFFSET 172
+    #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + 176)
+    #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + 688)
+    #define PPC_EXC_FPSCR_OFFSET 944
+    #define PPC_EXC_FRAME_SIZE 960
+    #define PPC_EXC_MIN_VSCR_OFFSET 92
+    #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + 96)
+    #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + 416)
+    #define PPC_EXC_MIN_FPSCR_OFFSET 528
+    #define CPU_INTERRUPT_FRAME_SIZE 544
+  #elif defined(PPC_MULTILIB_ALTIVEC)
+    #define PPC_EXC_VRSAVE_OFFSET 168
+    #define PPC_EXC_VSCR_OFFSET 172
+    #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + 176)
+    #define PPC_EXC_FRAME_SIZE 688
+    #define PPC_EXC_MIN_VSCR_OFFSET 92
+    #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + 96)
+    #define CPU_INTERRUPT_FRAME_SIZE 416
+  #elif defined(PPC_MULTILIB_FPU)
+    #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + 168)
+    #define PPC_EXC_FPSCR_OFFSET 424
+    #define PPC_EXC_FRAME_SIZE 448
+    #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + 96)
+    #define PPC_EXC_MIN_FPSCR_OFFSET 92
+    #define CPU_INTERRUPT_FRAME_SIZE 224
+  #else
+    #define PPC_EXC_FRAME_SIZE 176
+    #define CPU_INTERRUPT_FRAME_SIZE 96
+  #endif
+#else
+  #define PPC_EXC_SPEFSCR_OFFSET 36
+  #define PPC_EXC_ACC_OFFSET 40
+  #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 48)
+  #define PPC_EXC_VECTOR_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(4) + 4)
+  #define CPU_INTERRUPT_FRAME_SIZE 160
+  #define PPC_EXC_FRAME_SIZE 320
+#endif
+
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
 #ifdef RTEMS_SMP
@@ -32,6 +123,78 @@
 extern "C" {
 #endif
 
+typedef struct {
+  uint32_t FRAME_SP;
+  uint32_t FRAME_LR;
+  uint32_t EXC_SRR0;
+  uint32_t EXC_SRR1;
+  uint32_t unused;
+  uint32_t EXC_CR;
+  uint32_t EXC_CTR;
+  uint32_t EXC_XER;
+  uint32_t EXC_LR;
+  #ifdef __SPE__
+    uint32_t EXC_SPEFSCR;
+    uint64_t EXC_ACC;
+  #endif
+  PPC_GPR_TYPE GPR0;
+  PPC_GPR_TYPE GPR1;
+  PPC_GPR_TYPE GPR2;
+  PPC_GPR_TYPE GPR3;
+  PPC_GPR_TYPE GPR4;
+  PPC_GPR_TYPE GPR5;
+  PPC_GPR_TYPE GPR6;
+  PPC_GPR_TYPE GPR7;
+  PPC_GPR_TYPE GPR8;
+  PPC_GPR_TYPE GPR9;
+  PPC_GPR_TYPE GPR10;
+  PPC_GPR_TYPE GPR11;
+  PPC_GPR_TYPE GPR12;
+  uint32_t EARLY_INSTANT;
+  #ifdef PPC_MULTILIB_ALTIVEC
+    /* This field must take stvewx/lvewx requirements into account */
+    uint32_t VSCR;
+
+    uint8_t V0[16] RTEMS_ALIGNED(16);
+    uint8_t V1[16];
+    uint8_t V2[16];
+    uint8_t V3[16];
+    uint8_t V4[16];
+    uint8_t V5[16];
+    uint8_t V6[16];
+    uint8_t V7[16];
+    uint8_t V8[16];
+    uint8_t V9[16];
+    uint8_t V10[16];
+    uint8_t V11[16];
+    uint8_t V12[16];
+    uint8_t V13[16];
+    uint8_t V14[16];
+    uint8_t V15[16];
+    uint8_t V16[16];
+    uint8_t V17[16];
+    uint8_t V18[16];
+    uint8_t V19[16];
+  #endif
+  #ifdef PPC_MULTILIB_FPU
+    double F0;
+    double F1;
+    double F2;
+    double F3;
+    double F4;
+    double F5;
+    double F6;
+    double F7;
+    double F8;
+    double F9;
+    double F10;
+    double F11;
+    double F12;
+    double F13;
+    uint64_t FPSCR;
+  #endif
+} CPU_Interrupt_frame;
+
 #ifdef RTEMS_SMP
 
 static inline struct Per_CPU_Control *_PPC_Get_current_per_CPU_control( void )