From d343f830f4dae8e84b4b44902347c60cf18b2ffd Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue, 7 Aug 2018 06:58:34 +0200
Subject: tester: Exclude SMP build of some RISC-V BSPs

It makes no sense to build BSPs without support for atomic instructions
with SMP enabled.

Update #3433.
---
 tester/rtems/rtems-bsps-riscv.ini | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tester/rtems/rtems-bsps-riscv.ini b/tester/rtems/rtems-bsps-riscv.ini
index 986d639..da3a5a4 100644
--- a/tester/rtems/rtems-bsps-riscv.ini
+++ b/tester/rtems/rtems-bsps-riscv.ini
@@ -24,3 +24,4 @@
 bsps = rv32iac, rv32i, rv32imac, rv32imafc, rv32imafdc, rv32imafd, rv32im,
        rv64imac, rv64imac_medany, rv64imafdc, rv64imafd, rv64imafdc_medany,
        rv64imafd_medany
+exclude-smp = rv32i, rv32im
-- 
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