From 693e6b518d1710793096cdb11f806d9e511a8972 Mon Sep 17 00:00:00 2001
From: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk>
Date: Fri, 9 Nov 2018 10:21:08 +0000
Subject: rsb: Update RISC-V's Spike revision

---
 bare/config/devel/spike-1.1.0.cfg   |  4 ++--
 source-builder/config/spike-1-1.cfg | 20 ++++++++++----------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/bare/config/devel/spike-1.1.0.cfg b/bare/config/devel/spike-1.1.0.cfg
index 5b633fc..4e94189 100644
--- a/bare/config/devel/spike-1.1.0.cfg
+++ b/bare/config/devel/spike-1.1.0.cfg
@@ -10,10 +10,10 @@
 
 %define spike_version 1.1.0
 
-%hash sha512 priv-1.10.zip 46ff0a07135bdc8c442ade3727f080d09ec8e7136e42f082d135b256c06088dc0b9f34028f0a20bcb19bb6de5a144ea02a53c587fac4204f0f7d05a11ae23ed3
+%hash sha512 01252686902fa30665fbecfc1476d169ad1333d1.zip 7970f8dfc65ec5a5beab9effc755375d6c90eacc30a89261d9ab8cb4f1cf65c67cfb850e8c1a53302a860aae821e2869dcddd8c098da918bf944a3335edc71d5
 
 # RISC-V's front-end server (fesvr)
-%hash sha512 f683e01542acf60e50774d061bcb396b628e3e67.zip 54900159e4a4f6ec28a43702e651354932e22e1e1995fa82aeb182225fe32be085e850e6060b8feadf6ffdd6cbe19873a379af687e36d04a1a3ea337cef93b06
+%hash sha512 8d108a0a647901550d95925549337c2c3aec9ac8.zip 9b5ec44723fd96a961d93d369e50e6aeb327341b2dc42c17ed340d1bc0425511deb23fcf1e7c5926486c2a10bfc3cc6d6f4ceb0cda63590d46468db0ee2b1d3b
 
 #
 # The spike build instructions. We use 1.x.x Release 1.
diff --git a/source-builder/config/spike-1-1.cfg b/source-builder/config/spike-1-1.cfg
index ede6a42..17b4e2f 100644
--- a/source-builder/config/spike-1-1.cfg
+++ b/source-builder/config/spike-1-1.cfg
@@ -1,5 +1,5 @@
 #
-# RISC-V's spike (priv-1.10) 1.x.x Version 1.
+# RISC-V's spike (01252686902fa30665fbecfc1476d169ad1333d1) 1.x.x Version 1.
 #
 # This configuration file configure's, make's and install's RISC-V's spike simulator.
 #
@@ -17,8 +17,8 @@ URL: 	   https://github.com/riscv/riscv-isa-sim/
 #
 # Source
 #
-%source set spike https://github.com/riscv/riscv-isa-sim/archive/priv-1.10.zip
-%source set fesvr https://github.com/riscv/riscv-fesvr/archive/f683e01542acf60e50774d061bcb396b628e3e67.zip
+%source set spike https://github.com/riscv/riscv-isa-sim/archive/01252686902fa30665fbecfc1476d169ad1333d1.zip
+%source set fesvr https://github.com/riscv/riscv-fesvr/archive/8d108a0a647901550d95925549337c2c3aec9ac8.zip
 
 #
 # Prepare the source code.
@@ -26,25 +26,25 @@ URL: 	   https://github.com/riscv/riscv-isa-sim/
 %prep
   build_top=$(pwd)
 
-  %source setup fesvr -q -n riscv-fesvr-f683e01542acf60e50774d061bcb396b628e3e67
-  %source setup spike -q -n riscv-isa-sim-priv-1.10
+  %source setup fesvr -q -n riscv-fesvr-8d108a0a647901550d95925549337c2c3aec9ac8
+  %source setup spike -q -n riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1
 
   cd ${build_top}
 
 %build
   build_top=$(pwd)
 
-  cd riscv-fesvr-f683e01542acf60e50774d061bcb396b628e3e67
+  cd riscv-fesvr-8d108a0a647901550d95925549337c2c3aec9ac8
 
-  ../riscv-fesvr-f683e01542acf60e50774d061bcb396b628e3e67/configure \
+  ../riscv-fesvr-8d108a0a647901550d95925549337c2c3aec9ac8/configure \
   --prefix=%{_prefix}
   %{__make} %{?_smp_mflags} all$
   %{__make} install
 
 
-  cd ../riscv-isa-sim-priv-1.10
+  cd ../riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1
 
-  ../riscv-isa-sim-priv-1.10/configure \
+  ../riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1/configure \
   --prefix=%{_prefix} \
   --with-fesvr=%{_prefix}
 
@@ -57,7 +57,7 @@ URL: 	   https://github.com/riscv/riscv-isa-sim/
 
   rm -rf $SB_BUILD_ROOT
 
-  cd riscv-isa-sim-priv-1.10
+  cd riscv-isa-sim-01252686902fa30665fbecfc1476d169ad1333d1
   %{__make} DESTDIR=$SB_BUILD_ROOT PREFIX=%{_prefix} install
 
   cd ${build_top}
-- 
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