From 946611a1af848691477daa65839714e5e19da372 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 25 Nov 2014 13:14:46 +0100 Subject: e1000phy: Import from FreeBSD --- Makefile | 1 + freebsd-to-rtems.py | 2 + freebsd/sys/dev/mii/e1000phy.c | 503 ++++++++++++++++++++++++++++++++++++++ freebsd/sys/dev/mii/e1000phyreg.h | 374 ++++++++++++++++++++++++++++ 4 files changed, 880 insertions(+) create mode 100644 freebsd/sys/dev/mii/e1000phy.c create mode 100644 freebsd/sys/dev/mii/e1000phyreg.h diff --git a/Makefile b/Makefile index e692fadc..e5cb145a 100644 --- a/Makefile +++ b/Makefile @@ -399,6 +399,7 @@ LIB_C_FILES += freebsd/sys/dev/mii/mii.c LIB_C_FILES += freebsd/sys/dev/mii/mii_bitbang.c LIB_C_FILES += freebsd/sys/dev/mii/mii_physubr.c LIB_C_FILES += freebsd/sys/dev/mii/icsphy.c +LIB_C_FILES += freebsd/sys/dev/mii/e1000phy.c LIB_C_FILES += freebsd/sys/dev/mii/brgphy.c LIB_C_FILES += freebsd/sys/dev/tsec/if_tsec.c LIB_C_FILES += freebsd/sys/dev/cadence/if_cgem.c diff --git a/freebsd-to-rtems.py b/freebsd-to-rtems.py index bf3e61aa..b023f051 100755 --- a/freebsd-to-rtems.py +++ b/freebsd-to-rtems.py @@ -1244,6 +1244,7 @@ devNet.addKernelSpaceHeaderFiles( 'sys/dev/mii/mii_bitbang.h', 'sys/dev/mii/miivar.h', 'sys/dev/mii/brgphyreg.h', + 'sys/dev/mii/e1000phyreg.h', 'sys/dev/mii/icsphyreg.h', 'sys/dev/led/led.h', 'sys/net/bpf.h', @@ -1267,6 +1268,7 @@ devNet.addKernelSpaceSourceFiles( 'sys/dev/mii/mii_bitbang.c', 'sys/dev/mii/mii_physubr.c', 'sys/dev/mii/icsphy.c', + 'sys/dev/mii/e1000phy.c', 'sys/dev/mii/brgphy.c', 'sys/dev/tsec/if_tsec.c', 'sys/dev/cadence/if_cgem.c', diff --git a/freebsd/sys/dev/mii/e1000phy.c b/freebsd/sys/dev/mii/e1000phy.c new file mode 100644 index 00000000..822ebce4 --- /dev/null +++ b/freebsd/sys/dev/mii/e1000phy.c @@ -0,0 +1,503 @@ +#include + +/*- + * Principal Author: Parag Patel + * Copyright (c) 2001 + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Additional Copyright (c) 2001 by Traakan Software under same licence. + * Secondary Author: Matthew Jacob + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY. + */ + +/* + * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and + * 1000baseSX PHY. + * Nathan Binkert + * Jung-uk Kim + */ + +#include +#include +#include +#include +#include +#include + + +#include +#include + +#include +#include +#include + +#include + +#include + +static int e1000phy_probe(device_t); +static int e1000phy_attach(device_t); + +static device_method_t e1000phy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, e1000phy_probe), + DEVMETHOD(device_attach, e1000phy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + DEVMETHOD_END +}; + +static devclass_t e1000phy_devclass; +static driver_t e1000phy_driver = { + "e1000phy", + e1000phy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0); + +static int e1000phy_service(struct mii_softc *, struct mii_data *, int); +static void e1000phy_status(struct mii_softc *); +static void e1000phy_reset(struct mii_softc *); +static int e1000phy_mii_phy_auto(struct mii_softc *, int); + +static const struct mii_phydesc e1000phys[] = { + MII_PHY_DESC(MARVELL, E1000), + MII_PHY_DESC(MARVELL, E1011), + MII_PHY_DESC(MARVELL, E1000_3), + MII_PHY_DESC(MARVELL, E1000_5), + MII_PHY_DESC(MARVELL, E1111), + MII_PHY_DESC(xxMARVELL, E1000), + MII_PHY_DESC(xxMARVELL, E1011), + MII_PHY_DESC(xxMARVELL, E1000_3), + MII_PHY_DESC(xxMARVELL, E1000S), + MII_PHY_DESC(xxMARVELL, E1000_5), + MII_PHY_DESC(xxMARVELL, E1101), + MII_PHY_DESC(xxMARVELL, E3082), + MII_PHY_DESC(xxMARVELL, E1112), + MII_PHY_DESC(xxMARVELL, E1149), + MII_PHY_DESC(xxMARVELL, E1111), + MII_PHY_DESC(xxMARVELL, E1116), + MII_PHY_DESC(xxMARVELL, E1116R), + MII_PHY_DESC(xxMARVELL, E1118), + MII_PHY_DESC(xxMARVELL, E1149R), + MII_PHY_DESC(xxMARVELL, E3016), + MII_PHY_DESC(xxMARVELL, PHYG65G), + MII_PHY_END +}; + +static const struct mii_phy_funcs e1000phy_funcs = { + e1000phy_service, + e1000phy_status, + e1000phy_reset +}; + +static int +e1000phy_probe(device_t dev) +{ + + return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT)); +} + +static int +e1000phy_attach(device_t dev) +{ + struct mii_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + + mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &e1000phy_funcs, 0); + + ifp = sc->mii_pdata->mii_ifp; + if (strcmp(ifp->if_dname, "msk") == 0 && + (sc->mii_flags & MIIF_MACPRIV0) != 0) + sc->mii_flags |= MIIF_PHYPRIV0; + + switch (sc->mii_mpd_model) { + case MII_MODEL_xxMARVELL_E1011: + case MII_MODEL_xxMARVELL_E1112: + if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK) + sc->mii_flags |= MIIF_HAVEFIBER; + break; + case MII_MODEL_xxMARVELL_E1149: + case MII_MODEL_xxMARVELL_E1149R: + /* + * Some 88E1149 PHY's page select is initialized to + * point to other bank instead of copper/fiber bank + * which in turn resulted in wrong registers were + * accessed during PHY operation. It is believed that + * page 0 should be used for copper PHY so reinitialize + * E1000_EADR to select default copper PHY. If parent + * device know the type of PHY(either copper or fiber), + * that information should be used to select default + * type of PHY. + */ + PHY_WRITE(sc, E1000_EADR, 0); + break; + } + + PHY_RESET(sc); + + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; + if (sc->mii_capabilities & BMSR_EXTSTAT) + sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + return (0); +} + +static void +e1000phy_reset(struct mii_softc *sc) +{ + uint16_t reg, page; + + reg = PHY_READ(sc, E1000_SCR); + if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) { + reg &= ~E1000_SCR_AUTO_X_MODE; + PHY_WRITE(sc, E1000_SCR, reg); + if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) { + /* Select 1000BASE-X only mode. */ + page = PHY_READ(sc, E1000_EADR); + PHY_WRITE(sc, E1000_EADR, 2); + reg = PHY_READ(sc, E1000_SCR); + reg &= ~E1000_SCR_MODE_MASK; + reg |= E1000_SCR_MODE_1000BX; + PHY_WRITE(sc, E1000_SCR, reg); + if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) { + /* Set SIGDET polarity low for SFP module. */ + PHY_WRITE(sc, E1000_EADR, 1); + reg = PHY_READ(sc, E1000_SCR); + reg |= E1000_SCR_FIB_SIGDET_POLARITY; + PHY_WRITE(sc, E1000_SCR, reg); + } + PHY_WRITE(sc, E1000_EADR, page); + } + } else { + switch (sc->mii_mpd_model) { + case MII_MODEL_xxMARVELL_E1111: + case MII_MODEL_xxMARVELL_E1112: + case MII_MODEL_xxMARVELL_E1116: + case MII_MODEL_xxMARVELL_E1118: + case MII_MODEL_xxMARVELL_E1149: + case MII_MODEL_xxMARVELL_E1149R: + case MII_MODEL_xxMARVELL_PHYG65G: + /* Disable energy detect mode. */ + reg &= ~E1000_SCR_EN_DETECT_MASK; + reg |= E1000_SCR_AUTO_X_MODE; + if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116) + reg &= ~E1000_SCR_POWER_DOWN; + reg |= E1000_SCR_ASSERT_CRS_ON_TX; + break; + case MII_MODEL_xxMARVELL_E3082: + reg |= (E1000_SCR_AUTO_X_MODE >> 1); + reg |= E1000_SCR_ASSERT_CRS_ON_TX; + break; + case MII_MODEL_xxMARVELL_E3016: + reg |= E1000_SCR_AUTO_MDIX; + reg &= ~(E1000_SCR_EN_DETECT | + E1000_SCR_SCRAMBLER_DISABLE); + reg |= E1000_SCR_LPNP; + /* XXX Enable class A driver for Yukon FE+ A0. */ + PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001); + break; + default: + reg &= ~E1000_SCR_AUTO_X_MODE; + reg |= E1000_SCR_ASSERT_CRS_ON_TX; + break; + } + if (sc->mii_mpd_model != MII_MODEL_xxMARVELL_E3016) { + /* Auto correction for reversed cable polarity. */ + reg &= ~E1000_SCR_POLARITY_REVERSAL; + } + PHY_WRITE(sc, E1000_SCR, reg); + + if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 || + sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 || + sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) { + PHY_WRITE(sc, E1000_EADR, 2); + reg = PHY_READ(sc, E1000_SCR); + reg |= E1000_SCR_RGMII_POWER_UP; + PHY_WRITE(sc, E1000_SCR, reg); + PHY_WRITE(sc, E1000_EADR, 0); + } + } + + switch (sc->mii_mpd_model) { + case MII_MODEL_xxMARVELL_E3082: + case MII_MODEL_xxMARVELL_E1112: + case MII_MODEL_xxMARVELL_E1118: + break; + case MII_MODEL_xxMARVELL_E1116: + page = PHY_READ(sc, E1000_EADR); + /* Select page 3, LED control register. */ + PHY_WRITE(sc, E1000_EADR, 3); + PHY_WRITE(sc, E1000_SCR, + E1000_SCR_LED_LOS(1) | /* Link/Act */ + E1000_SCR_LED_INIT(8) | /* 10Mbps */ + E1000_SCR_LED_STAT1(7) | /* 100Mbps */ + E1000_SCR_LED_STAT0(7)); /* 1000Mbps */ + /* Set blink rate. */ + PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) | + E1000_BLINK_RATE(E1000_BLINK_84MS)); + PHY_WRITE(sc, E1000_EADR, page); + break; + case MII_MODEL_xxMARVELL_E3016: + /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */ + PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04); + /* Integrated register calibration workaround. */ + PHY_WRITE(sc, 0x1D, 17); + PHY_WRITE(sc, 0x1E, 0x3F60); + break; + default: + /* Force TX_CLK to 25MHz clock. */ + reg = PHY_READ(sc, E1000_ESCR); + reg |= E1000_ESCR_TX_CLK_25; + PHY_WRITE(sc, E1000_ESCR, reg); + break; + } + + /* Reset the PHY so all changes take effect. */ + reg = PHY_READ(sc, E1000_CR); + reg |= E1000_CR_RESET; + PHY_WRITE(sc, E1000_CR, reg); +} + +static int +e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + uint16_t speed, gig; + int reg; + + switch (cmd) { + case MII_POLLSTAT: + break; + + case MII_MEDIACHG: + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { + e1000phy_mii_phy_auto(sc, ife->ifm_media); + break; + } + + speed = 0; + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_1000_T: + if ((sc->mii_extcapabilities & + (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0) + return (EINVAL); + speed = E1000_CR_SPEED_1000; + break; + case IFM_1000_SX: + if ((sc->mii_extcapabilities & + (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) + return (EINVAL); + speed = E1000_CR_SPEED_1000; + break; + case IFM_100_TX: + speed = E1000_CR_SPEED_100; + break; + case IFM_10_T: + speed = E1000_CR_SPEED_10; + break; + case IFM_NONE: + reg = PHY_READ(sc, E1000_CR); + PHY_WRITE(sc, E1000_CR, + reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); + goto done; + default: + return (EINVAL); + } + + if ((ife->ifm_media & IFM_FDX) != 0) { + speed |= E1000_CR_FULL_DUPLEX; + gig = E1000_1GCR_1000T_FD; + } else + gig = E1000_1GCR_1000T; + + reg = PHY_READ(sc, E1000_CR); + reg &= ~E1000_CR_AUTO_NEG_ENABLE; + PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET); + + if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { + gig |= E1000_1GCR_MS_ENABLE; + if ((ife->ifm_media & IFM_ETH_MASTER) != 0) + gig |= E1000_1GCR_MS_VALUE; + } else if ((sc->mii_extcapabilities & + (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) + gig = 0; + PHY_WRITE(sc, E1000_1GCR, gig); + PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); + PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET); +done: + break; + case MII_TICK: + /* + * Is the interface even up? + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return (0); + + /* + * Only used for autonegotiation. + */ + if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { + sc->mii_ticks = 0; + break; + } + + /* + * check for link. + * Read the status register twice; BMSR_LINK is latch-low. + */ + reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); + if (reg & BMSR_LINK) { + sc->mii_ticks = 0; + break; + } + + /* Announce link loss right after it happens. */ + if (sc->mii_ticks++ == 0) + break; + if (sc->mii_ticks <= sc->mii_anegticks) + break; + + sc->mii_ticks = 0; + PHY_RESET(sc); + e1000phy_mii_phy_auto(sc, ife->ifm_media); + break; + } + + /* Update the media status. */ + PHY_STATUS(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} + +static void +e1000phy_status(struct mii_softc *sc) +{ + struct mii_data *mii = sc->mii_pdata; + int bmcr, bmsr, ssr; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); + bmcr = PHY_READ(sc, E1000_CR); + ssr = PHY_READ(sc, E1000_SSR); + + if (bmsr & E1000_SR_LINK_STATUS) + mii->mii_media_status |= IFM_ACTIVE; + + if (bmcr & E1000_CR_LOOPBACK) + mii->mii_media_active |= IFM_LOOP; + + if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && + (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) { + /* Erg, still trying, I guess... */ + mii->mii_media_active |= IFM_NONE; + return; + } + + if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { + switch (ssr & E1000_SSR_SPEED) { + case E1000_SSR_1000MBS: + mii->mii_media_active |= IFM_1000_T; + break; + case E1000_SSR_100MBS: + mii->mii_media_active |= IFM_100_TX; + break; + case E1000_SSR_10MBS: + mii->mii_media_active |= IFM_10_T; + break; + default: + mii->mii_media_active |= IFM_NONE; + return; + } + } else { + /* + * Some fiber PHY(88E1112) does not seem to set resolved + * speed so always assume we've got IFM_1000_SX. + */ + mii->mii_media_active |= IFM_1000_SX; + } + + if (ssr & E1000_SSR_DUPLEX) { + mii->mii_media_active |= IFM_FDX; + if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) + mii->mii_media_active |= mii_phy_flowstatus(sc); + } else + mii->mii_media_active |= IFM_HDX; + + if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { + if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) & + E1000_1GSR_MS_CONFIG_RES) != 0) + mii->mii_media_active |= IFM_ETH_MASTER; + } +} + +static int +e1000phy_mii_phy_auto(struct mii_softc *sc, int media) +{ + uint16_t reg; + + if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { + reg = PHY_READ(sc, E1000_AR); + reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR); + reg |= E1000_AR_10T | E1000_AR_10T_FD | + E1000_AR_100TX | E1000_AR_100TX_FD; + if ((media & IFM_FLOW) != 0 || + (sc->mii_flags & MIIF_FORCEPAUSE) != 0) + reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR; + PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); + } else + PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X); + if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) + PHY_WRITE(sc, E1000_1GCR, + E1000_1GCR_1000T_FD | E1000_1GCR_1000T); + PHY_WRITE(sc, E1000_CR, + E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG); + + return (EJUSTRETURN); +} diff --git a/freebsd/sys/dev/mii/e1000phyreg.h b/freebsd/sys/dev/mii/e1000phyreg.h new file mode 100644 index 00000000..e5d5cf96 --- /dev/null +++ b/freebsd/sys/dev/mii/e1000phyreg.h @@ -0,0 +1,374 @@ +/* $FreeBSD$ */ +/*- + * Principal Author: Parag Patel + * Copyright (c) 2001 + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Additional Copyright (c) 2001 by Traakan Software under same licence. + * Secondary Author: Matthew Jacob + */ + +/*- + * Derived by information released by Intel under the following license: + * + * Copyright (c) 1999 - 2001, Intel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * Marvell E1000 PHY registers + */ + +#define E1000_MAX_REG_ADDRESS 0x1F + +#define E1000_CR 0x00 /* control register */ +#define E1000_CR_SPEED_SELECT_MSB 0x0040 +#define E1000_CR_COLL_TEST_ENABLE 0x0080 +#define E1000_CR_FULL_DUPLEX 0x0100 +#define E1000_CR_RESTART_AUTO_NEG 0x0200 +#define E1000_CR_ISOLATE 0x0400 +#define E1000_CR_POWER_DOWN 0x0800 +#define E1000_CR_AUTO_NEG_ENABLE 0x1000 +#define E1000_CR_SPEED_SELECT_LSB 0x2000 +#define E1000_CR_LOOPBACK 0x4000 +#define E1000_CR_RESET 0x8000 + +#define E1000_CR_SPEED_1000 0x0040 +#define E1000_CR_SPEED_100 0x2000 +#define E1000_CR_SPEED_10 0x0000 + +#define E1000_SR 0x01 /* status register */ +#define E1000_SR_EXTENDED 0x0001 +#define E1000_SR_JABBER_DETECT 0x0002 +#define E1000_SR_LINK_STATUS 0x0004 +#define E1000_SR_AUTO_NEG 0x0008 +#define E1000_SR_REMOTE_FAULT 0x0010 +#define E1000_SR_AUTO_NEG_COMPLETE 0x0020 +#define E1000_SR_PREAMBLE_SUPPRESS 0x0040 +#define E1000_SR_EXTENDED_STATUS 0x0100 +#define E1000_SR_100T2 0x0200 +#define E1000_SR_100T2_FD 0x0400 +#define E1000_SR_10T 0x0800 +#define E1000_SR_10T_FD 0x1000 +#define E1000_SR_100TX 0x2000 +#define E1000_SR_100TX_FD 0x4000 +#define E1000_SR_100T4 0x8000 + +#define E1000_ID1 0x02 /* ID register 1 */ +#define E1000_ID2 0x03 /* ID register 2 */ +#define E1000_ID_88E1000 0x01410C50 +#define E1000_ID_88E1000S 0x01410C40 +#define E1000_ID_88E1011 0x01410C20 +#define E1000_ID_MASK 0xFFFFFFF0 + +#define E1000_AR 0x04 /* autonegotiation advertise reg */ +#define E1000_AR_SELECTOR_FIELD 0x0001 +#define E1000_AR_10T 0x0020 +#define E1000_AR_10T_FD 0x0040 +#define E1000_AR_100TX 0x0080 +#define E1000_AR_100TX_FD 0x0100 +#define E1000_AR_100T4 0x0200 +#define E1000_AR_PAUSE 0x0400 +#define E1000_AR_ASM_DIR 0x0800 +#define E1000_AR_REMOTE_FAULT 0x2000 +#define E1000_AR_NEXT_PAGE 0x8000 +#define E1000_AR_SPEED_MASK 0x01E0 + +/* Autonegotiation register bits for fiber cards (Alaska Only!) */ +#define E1000_FA_1000X_FD 0x0020 +#define E1000_FA_1000X 0x0040 +#define E1000_FA_SYM_PAUSE 0x0080 +#define E1000_FA_ASYM_PAUSE 0x0100 +#define E1000_FA_FAULT1 0x1000 +#define E1000_FA_FAULT2 0x2000 +#define E1000_FA_NEXT_PAGE 0x8000 + +#define E1000_LPAR 0x05 /* autoneg link partner abilities reg */ +#define E1000_LPAR_SELECTOR_FIELD 0x0001 +#define E1000_LPAR_10T 0x0020 +#define E1000_LPAR_10T_FD 0x0040 +#define E1000_LPAR_100TX 0x0080 +#define E1000_LPAR_100TX_FD 0x0100 +#define E1000_LPAR_100T4 0x0200 +#define E1000_LPAR_PAUSE 0x0400 +#define E1000_LPAR_ASM_DIR 0x0800 +#define E1000_LPAR_REMOTE_FAULT 0x2000 +#define E1000_LPAR_ACKNOWLEDGE 0x4000 +#define E1000_LPAR_NEXT_PAGE 0x8000 + +/* autoneg link partner ability register bits for fiber cards (Alaska Only!) */ +#define E1000_FPAR_1000X_FD 0x0020 +#define E1000_FPAR_1000X 0x0040 +#define E1000_FPAR_SYM_PAUSE 0x0080 +#define E1000_FPAR_ASYM_PAUSE 0x0100 +#define E1000_FPAR_FAULT1 0x1000 +#define E1000_FPAR_FAULT2 0x2000 +#define E1000_FPAR_ACK 0x4000 +#define E1000_FPAR_NEXT_PAGE 0x8000 + +#define E1000_ER 0x06 /* autoneg expansion reg */ +#define E1000_ER_LP_NWAY 0x0001 +#define E1000_ER_PAGE_RXD 0x0002 +#define E1000_ER_NEXT_PAGE 0x0004 +#define E1000_ER_LP_NEXT_PAGE 0x0008 +#define E1000_ER_PAR_DETECT_FAULT 0x0100 + +#define E1000_NPTX 0x07 /* autoneg next page TX */ +#define E1000_NPTX_MSG_CODE_FIELD 0x0001 +#define E1000_NPTX_TOGGLE 0x0800 +#define E1000_NPTX_ACKNOWLDGE2 0x1000 +#define E1000_NPTX_MSG_PAGE 0x2000 +#define E1000_NPTX_NEXT_PAGE 0x8000 + +#define E1000_RNPR 0x08 /* autoneg link-partner (?) next page */ +#define E1000_RNPR_MSG_CODE_FIELD 0x0001 +#define E1000_RNPR_TOGGLE 0x0800 +#define E1000_RNPR_ACKNOWLDGE2 0x1000 +#define E1000_RNPR_MSG_PAGE 0x2000 +#define E1000_RNPR_ACKNOWLDGE 0x4000 +#define E1000_RNPR_NEXT_PAGE 0x8000 + +#define E1000_1GCR 0x09 /* 1000T (1G) control reg */ +#define E1000_1GCR_ASYM_PAUSE 0x0080 +#define E1000_1GCR_1000T 0x0100 +#define E1000_1GCR_1000T_FD 0x0200 +#define E1000_1GCR_REPEATER_DTE 0x0400 +#define E1000_1GCR_MS_VALUE 0x0800 +#define E1000_1GCR_MS_ENABLE 0x1000 +#define E1000_1GCR_TEST_MODE_NORMAL 0x0000 +#define E1000_1GCR_TEST_MODE_1 0x2000 +#define E1000_1GCR_TEST_MODE_2 0x4000 +#define E1000_1GCR_TEST_MODE_3 0x6000 +#define E1000_1GCR_TEST_MODE_4 0x8000 +#define E1000_1GCR_SPEED_MASK 0x0300 + +#define E1000_1GSR 0x0A /* 1000T (1G) status reg */ +#define E1000_1GSR_IDLE_ERROR_CNT 0x0000 +#define E1000_1GSR_ASYM_PAUSE_DIR 0x0100 +#define E1000_1GSR_LP 0x0400 +#define E1000_1GSR_LP_FD 0x0800 +#define E1000_1GSR_REMOTE_RX_STATUS 0x1000 +#define E1000_1GSR_LOCAL_RX_STATUS 0x2000 +#define E1000_1GSR_MS_CONFIG_RES 0x4000 +#define E1000_1GSR_MS_CONFIG_FAULT 0x8000 + +#define E1000_ESR 0x0F /* IEEE extended status reg */ +#define E1000_ESR_1000T 0x1000 +#define E1000_ESR_1000T_FD 0x2000 +#define E1000_ESR_1000X 0x4000 +#define E1000_ESR_1000X_FD 0x8000 + +#define E1000_TX_POLARITY_MASK 0x0100 +#define E1000_TX_NORMAL_POLARITY 0 + +#define E1000_AUTO_POLARITY_DISABLE 0x0010 + +#define E1000_SCR 0x10 /* special control register */ +#define E1000_SCR_JABBER_DISABLE 0x0001 +#define E1000_SCR_POLARITY_REVERSAL 0x0002 +#define E1000_SCR_SQE_TEST 0x0004 +#define E1000_SCR_INT_FIFO_DISABLE 0x0008 +#define E1000_SCR_CLK125_DISABLE 0x0010 +#define E1000_SCR_MDI_MANUAL_MODE 0x0000 +#define E1000_SCR_MDIX_MANUAL_MODE 0x0020 +#define E1000_SCR_AUTO_X_1000T 0x0040 +#define E1000_SCR_AUTO_X_MODE 0x0060 +#define E1000_SCR_10BT_EXT_ENABLE 0x0080 +#define E1000_SCR_MII_5BIT_ENABLE 0x0100 +#define E1000_SCR_SCRAMBLER_DISABLE 0x0200 +#define E1000_SCR_FORCE_LINK_GOOD 0x0400 +#define E1000_SCR_ASSERT_CRS_ON_TX 0x0800 +#define E1000_SCR_RX_FIFO_DEPTH_6 0x0000 +#define E1000_SCR_RX_FIFO_DEPTH_8 0x1000 +#define E1000_SCR_RX_FIFO_DEPTH_10 0x2000 +#define E1000_SCR_RX_FIFO_DEPTH_12 0x3000 +#define E1000_SCR_TX_FIFO_DEPTH_6 0x0000 +#define E1000_SCR_TX_FIFO_DEPTH_8 0x4000 +#define E1000_SCR_TX_FIFO_DEPTH_10 0x8000 +#define E1000_SCR_TX_FIFO_DEPTH_12 0xC000 + +/* 88E3016 only */ +#define E1000_SCR_AUTO_MDIX 0x0030 +#define E1000_SCR_SIGDET_POLARITY 0x0040 +#define E1000_SCR_EXT_DISTANCE 0x0080 +#define E1000_SCR_FEFI_DISABLE 0x0100 +#define E1000_SCR_NLP_GEN_DISABLE 0x0800 +#define E1000_SCR_LPNP 0x1000 +#define E1000_SCR_NLP_CHK_DISABLE 0x2000 +#define E1000_SCR_EN_DETECT 0x4000 + +#define E1000_SCR_EN_DETECT_MASK 0x0300 + +/* 88E1112 page 1 fiber specific control */ +#define E1000_SCR_FIB_TX_DIS 0x0008 +#define E1000_SCR_FIB_SIGDET_POLARITY 0x0200 +#define E1000_SCR_FIB_FORCE_LINK 0x0400 + +/* 88E1112 page 2 */ +#define E1000_SCR_MODE_MASK 0x0380 +#define E1000_SCR_MODE_AUTO 0x0180 +#define E1000_SCR_MODE_COPPER 0x0280 +#define E1000_SCR_MODE_1000BX 0x0380 + +/* 88E1116 page 0 */ +#define E1000_SCR_POWER_DOWN 0x0004 +/* 88E1116, 88E1149 page 2 */ +#define E1000_SCR_RGMII_POWER_UP 0x0008 + +/* 88E1116, 88E1149 page 3 */ +#define E1000_SCR_LED_STAT0_MASK 0x000F +#define E1000_SCR_LED_STAT1_MASK 0x00F0 +#define E1000_SCR_LED_INIT_MASK 0x0F00 +#define E1000_SCR_LED_LOS_MASK 0xF000 +#define E1000_SCR_LED_STAT0(x) ((x) & E1000_SCR_LED_STAT0_MASK) +#define E1000_SCR_LED_STAT1(x) ((x) & E1000_SCR_LED_STAT1_MASK) +#define E1000_SCR_LED_INIT(x) ((x) & E1000_SCR_LED_INIT_MASK) +#define E1000_SCR_LED_LOS(x) ((x) & E1000_SCR_LED_LOS_MASK) + +#define E1000_SSR 0x11 /* special status register */ +#define E1000_SSR_JABBER 0x0001 +#define E1000_SSR_REV_POLARITY 0x0002 +#define E1000_SSR_MDIX 0x0020 +#define E1000_SSR_LINK 0x0400 +#define E1000_SSR_SPD_DPLX_RESOLVED 0x0800 +#define E1000_SSR_PAGE_RCVD 0x1000 +#define E1000_SSR_DUPLEX 0x2000 +#define E1000_SSR_SPEED 0xC000 +#define E1000_SSR_10MBS 0x0000 +#define E1000_SSR_100MBS 0x4000 +#define E1000_SSR_1000MBS 0x8000 + +#define E1000_IER 0x12 /* interrupt enable reg */ +#define E1000_IER_JABBER 0x0001 +#define E1000_IER_POLARITY_CHANGE 0x0002 +#define E1000_IER_MDIX_CHANGE 0x0040 +#define E1000_IER_FIFO_OVER_UNDERUN 0x0080 +#define E1000_IER_FALSE_CARRIER 0x0100 +#define E1000_IER_SYMBOL_ERROR 0x0200 +#define E1000_IER_LINK_STAT_CHANGE 0x0400 +#define E1000_IER_AUTO_NEG_COMPLETE 0x0800 +#define E1000_IER_PAGE_RECEIVED 0x1000 +#define E1000_IER_DUPLEX_CHANGED 0x2000 +#define E1000_IER_SPEED_CHANGED 0x4000 +#define E1000_IER_AUTO_NEG_ERR 0x8000 + +/* 88E1116, 88E1149 page 3, LED timer control. */ +#define E1000_PULSE_MASK 0x7000 +#define E1000_PULSE_NO_STR 0 /* no pulse stretching */ +#define E1000_PULSE_21MS 1 /* 21 ms to 42 ms */ +#define E1000_PULSE_42MS 2 /* 42 ms to 84 ms */ +#define E1000_PULSE_84MS 3 /* 84 ms to 170 ms */ +#define E1000_PULSE_170MS 4 /* 170 ms to 340 ms */ +#define E1000_PULSE_340MS 5 /* 340 ms to 670 ms */ +#define E1000_PULSE_670MS 6 /* 670 ms to 1300 ms */ +#define E1000_PULSE_1300MS 7 /* 1300 ms to 2700 ms */ +#define E1000_PULSE_DUR(x) ((x) & E1000_PULSE_MASK) + +#define E1000_BLINK_MASK 0x0700 +#define E1000_BLINK_42MS 0 /* 42 ms */ +#define E1000_BLINK_84MS 1 /* 84 ms */ +#define E1000_BLINK_170MS 2 /* 170 ms */ +#define E1000_BLINK_340MS 3 /* 340 ms */ +#define E1000_BLINK_670MS 4 /* 670 ms */ +#define E1000_BLINK_RATE(x) ((x) & E1000_BLINK_MASK) + +#define E1000_ISR 0x13 /* interrupt status reg */ +#define E1000_ISR_JABBER 0x0001 +#define E1000_ISR_POLARITY_CHANGE 0x0002 +#define E1000_ISR_MDIX_CHANGE 0x0040 +#define E1000_ISR_FIFO_OVER_UNDERUN 0x0080 +#define E1000_ISR_FALSE_CARRIER 0x0100 +#define E1000_ISR_SYMBOL_ERROR 0x0200 +#define E1000_ISR_LINK_STAT_CHANGE 0x0400 +#define E1000_ISR_AUTO_NEG_COMPLETE 0x0800 +#define E1000_ISR_PAGE_RECEIVED 0x1000 +#define E1000_ISR_DUPLEX_CHANGED 0x2000 +#define E1000_ISR_SPEED_CHANGED 0x4000 +#define E1000_ISR_AUTO_NEG_ERR 0x8000 + +#define E1000_ESCR 0x14 /* extended special control reg */ +#define E1000_ESCR_FIBER_LOOPBACK 0x4000 +#define E1000_ESCR_DOWN_NO_IDLE 0x8000 +#define E1000_ESCR_TX_CLK_2_5 0x0060 +#define E1000_ESCR_TX_CLK_25 0x0070 +#define E1000_ESCR_TX_CLK_0 0x0000 + +#define E1000_RECR 0x15 /* RX error counter reg */ + +#define E1000_EADR 0x16 /* extended address reg */ + +#define E1000_LCR 0x18 /* LED control reg */ +#define E1000_LCR_LED_TX 0x0001 +#define E1000_LCR_LED_RX 0x0002 +#define E1000_LCR_LED_DUPLEX 0x0004 +#define E1000_LCR_LINK 0x0008 +#define E1000_LCR_BLINK_42MS 0x0000 +#define E1000_LCR_BLINK_84MS 0x0100 +#define E1000_LCR_BLINK_170MS 0x0200 +#define E1000_LCR_BLINK_340MS 0x0300 +#define E1000_LCR_BLINK_670MS 0x0400 +#define E1000_LCR_PULSE_OFF 0x0000 +#define E1000_LCR_PULSE_21_42MS 0x1000 +#define E1000_LCR_PULSE_42_84MS 0x2000 +#define E1000_LCR_PULSE_84_170MS 0x3000 +#define E1000_LCR_PULSE_170_340MS 0x4000 +#define E1000_LCR_PULSE_340_670MS 0x5000 +#define E1000_LCR_PULSE_670_13S 0x6000 +#define E1000_LCR_PULSE_13_26S 0x7000 + +/* The following register is found only on the 88E1011 Alaska PHY */ +#define E1000_ESSR 0x1B /* Extended PHY specific sts */ +#define E1000_ESSR_FIBER_LINK 0x2000 +#define E1000_ESSR_GMII_COPPER 0x000f +#define E1000_ESSR_GMII_FIBER 0x0007 +#define E1000_ESSR_TBI_COPPER 0x000d +#define E1000_ESSR_TBI_FIBER 0x0005 -- cgit v1.2.3