diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-09-07 08:34:34 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-09-11 10:53:38 +0200 |
| commit | 7f5afa04cdff28fa2afa6e7df1c2f88289e0f4ac (patch) | |
| tree | bd04facbac20b09e8b2448d3186e664760d2008c | |
| parent | if_dwc: Invalidate read buffer again (diff) | |
| download | rtems-libbsd-7f5afa04cdff28fa2afa6e7df1c2f88289e0f4ac.tar.bz2 | |
if_dwc: Fix a possible interrupt starvation
| -rw-r--r-- | freebsd/sys/dev/dwc/if_dwc.c | 27 | ||||
| -rw-r--r-- | freebsd/sys/dev/dwc/if_dwc.h | 1 |
2 files changed, 13 insertions, 15 deletions
diff --git a/freebsd/sys/dev/dwc/if_dwc.c b/freebsd/sys/dev/dwc/if_dwc.c index 359226de..a3716a15 100644 --- a/freebsd/sys/dev/dwc/if_dwc.c +++ b/freebsd/sys/dev/dwc/if_dwc.c @@ -1014,25 +1014,22 @@ dwc_intr(void *arg) } reg = READ4(sc, DMA_STATUS); - if (reg & DMA_STATUS_NIS) { - if (reg & DMA_STATUS_RI) - dwc_rxfinish_locked(sc); + WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); - if (reg & DMA_STATUS_TI) - dwc_txfinish_locked(sc); - } + if (reg & (DMA_STATUS_RI | DMA_STATUS_RU)) + dwc_rxfinish_locked(sc); - if (reg & DMA_STATUS_AIS) { - if (reg & DMA_STATUS_FBI) { - /* Fatal bus error */ - device_printf(sc->dev, - "Ethernet DMA error, restarting controller.\n"); - dwc_stop_locked(sc); - dwc_init_locked(sc); - } + if (reg & DMA_STATUS_TI) + dwc_txfinish_locked(sc); + + if (reg & DMA_STATUS_FBI) { + /* Fatal bus error */ + device_printf(sc->dev, + "Ethernet DMA error, restarting controller.\n"); + dwc_stop_locked(sc); + dwc_init_locked(sc); } - WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); DWC_UNLOCK(sc); } diff --git a/freebsd/sys/dev/dwc/if_dwc.h b/freebsd/sys/dev/dwc/if_dwc.h index aa5c9734..2ba9860e 100644 --- a/freebsd/sys/dev/dwc/if_dwc.h +++ b/freebsd/sys/dev/dwc/if_dwc.h @@ -220,6 +220,7 @@ #define DMA_STATUS_NIS (1 << 16) #define DMA_STATUS_AIS (1 << 15) #define DMA_STATUS_FBI (1 << 13) +#define DMA_STATUS_RU (1 << 7) #define DMA_STATUS_RI (1 << 6) #define DMA_STATUS_TI (1 << 0) #define DMA_STATUS_INTR_MASK 0x1ffff |