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authorSebastian Huber <sebastian.huber@embedded-brains.de>2018-02-05 16:45:20 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2018-02-06 09:56:35 +0100
commit138bf250c2b2029ab9bb100c65d8ff43c698cf06 (patch)
tree32e3ee08373730b330a3983d5f3174217dcfba43
parentAdd device tree support for Altera/Intel Cyclone V (diff)
downloadrtems-libbsd-138bf250c2b2029ab9bb100c65d8ff43c698cf06.tar.bz2
dw_mmc: Add MMCBR_IVAR_TIMING
-rw-r--r--rtemsbsd/sys/dev/dw_mmc/dw_mmc.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/rtemsbsd/sys/dev/dw_mmc/dw_mmc.c b/rtemsbsd/sys/dev/dw_mmc/dw_mmc.c
index c4e3130b..a65879e7 100644
--- a/rtemsbsd/sys/dev/dw_mmc/dw_mmc.c
+++ b/rtemsbsd/sys/dev/dw_mmc/dw_mmc.c
@@ -1039,6 +1039,9 @@ dw_mmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
case MMCBR_IVAR_CAPS:
*(int *)result = sc->host.caps;
break;
+ case MMCBR_IVAR_TIMING:
+ *result = sc->host.ios.timing;
+ break;
case MMCBR_IVAR_MAX_DATA:
*(int *)result = 1;
break;
@@ -1078,6 +1081,9 @@ dw_mmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
case MMCBR_IVAR_VDD:
sc->host.ios.vdd = value;
break;
+ case MMCBR_IVAR_TIMING:
+ sc->host.ios.timing = value;
+ break;
/* These are read-only */
case MMCBR_IVAR_CAPS:
case MMCBR_IVAR_HOST_OCR: